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| this is information on a product in full production. september 2012 doc id 022508 rev 2 1/113 1 spear320s embedded mpu with arm926 core for industrial and consumer applications datasheet ? production data features arm926ej-s cpu core, up to 333 mhz multilayer bus matrix, up to 166 mhz internal memories: 32 kb rom, 8 kb sram memory interfaces: ? ddr controller (ddr2-666, lpddr-333), 8-/16-bit ? serial nor flash controller ? parallel nand flash controller, 8-/16-bit data bus ? parallel nor flash/fpga interface, 8-/16-bit data bus connectivity: ? 2 x usb 2.0 host ports (integrated phy) ? 1 x usb 2.0 device port (integrated phy) ? 2 x fast ethernet ports (external mii/rmii phy) ? 1 x mmc-sd card/sdio controller ? 2 x can 2.0 ports ?7 x uart ports ? 3 x i2c ports: master/slave ? 3 x synchronous serial ports, spi/microwire/ti protocols, master/slave ? 1 x rs485 interface ? 1 x fast irda interface ? 1 x legacy parallel port (ieee 1284), slave mode ? 10-bit adc, 8 channels, 1 msps ? up to 102 gpios with interrupt capability hmi support: ? lcd display controller, up to xga (1024 x 768, 24 bpp) ? resistive touchscreen interface ? jpeg codec accelerator ? 1 x i2s digital audio port security ? cryptographic co-processor miscellaneous functions: ? system controller, vectored interrupt controller, watchdog, real-time clock ? dynamic power-saving features ? 8-channel dma controller ? 6 x 16-bit general purpose timers with prescaler and 4 capture inputs ? 4 x pwm generators ? debug and trace interfaces: jtag/etm applications the spear320s embedded mpu is configurable for a range of industrial and consumer applications such as: human machine interface (hmi) terminals factory automation / plcs medical equipment smart energy meters and gateways voip phones small printers the device is hardware-compliant to the support of both real-time (rtos) and high-level (hlos) operating systems, such as linux and windows embedded compact 7. table 1. device summary order code temp range, c package packing SPEAR320S-2 -40 to 85 lfbga289 (15x15 mm, pitch 0.8 mm) tr ay lfbga289 (15 x 15 x 1.7 mm) www. s t.com
contents spear320s 2/113 doc id 022508 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 device functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 cpu subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 internal memories (bootrom/sram) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 multiport ddr controller (mpmc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4 serial nor flash controller (smi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5 parallel nand flash controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 external memory interface (emi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7 usb 2.0 host ports (uhc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8 usb 2.0 device port (udc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9 fast ethernet ports (mii/rmii) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9.1 mii0 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9.2 rmii0 and mii1/rmii1 ethernet controllers . . . . . . . . . . . . . . . . . . . . . . 17 2.10 mmc-sd card/sdio controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11 can 2.0 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.12 asynchronous serial ports (uart) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13 i2c bus ports (i2c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.14 synchronous serial ports (ssp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.15 rs485 port (rs485) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.16 fast infrared port (irda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.17 legacy ieee 1284 parallel port (spp) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.18 a/d converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.19 general purpose i/os (gpio/xgpio) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.20 lcd display controller (clcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.21 touchscreen interface (touchscreen) . . . . . . . . . . . . . . . . . . . . . . . . 23 2.22 jpeg codec accelerator (jpgc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.23 digital audio port (i2s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.24 cryptographic co-processor (c3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.25 system controller (sysctr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.25.1 reset and clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 spear320s contents doc id 022508 rev 2 3/113 2.26 vectored interrupt controller (vic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.27 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.28 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.29 dma controller (dmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.30 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.31 pulse width modulators (pwm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.1 pin/ball map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2 required external components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3 dedicated pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.1 clock, reset and 3v3 comparator pins . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.3.2 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3.3 debug pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.4 non-multiplexed pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.4 shared io pins (pl_gpios) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.1 pl_gpio / pl_clk pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.4.2 extended mode: rmii automation networking mode . . . . . . . . . . . . . . . 37 3.4.3 alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.4 legacy configuration modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3.4.5 boot pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4.6 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.4.7 multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.4.8 multiplexed signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.5 pl_gpio and pl_clk pin sharing for debug and test modes . . . . . . . . 66 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.2 maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.4 overshoot and undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4.5 3.3v i/o characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 4.6 clocking parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.6.1 master clock (mclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.6.2 real-time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 contents spear320s 4/113 doc id 022508 rev 2 4.7 lpddr and ddr2 pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4.8 adc pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 4.9 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.10 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 4.11 reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5 timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.1 external interrupt timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.2 reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 5.3 can timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5.4 clcd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 5.5 ddr2/lpddr timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5.5.1 ddr2/lpddr read cycle timing characteristics . . . . . . . . . . . . . . . . . . 81 5.5.2 ddr2/lpddr write cycle timing characteristics . . . . . . . . . . . . . . . . . . 82 5.5.3 ddr2/lpddr command timing characteristics . . . . . . . . . . . . . . . . . . 82 5.6 emi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 5.7 ethernet mii timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.7.1 mii transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 5.7.2 mii receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.7.3 mdc/mdio timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 5.8 ethernet rmii timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.8.1 rmii transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.8.2 rmii receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 5.9 fsmc timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 5.10 gpio/xgpio timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 5.11 i 2 c timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5.12 i2s timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.13 pwm timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 5.14 sd timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 5.15 smi timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 5.16 ssp timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.16.1 spi master mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5.16.2 spi slave mode timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 5.17 spp timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 spear320s contents doc id 022508 rev 2 5/113 5.18 uart timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 6 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 appendix a acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 list of tables spear320s 6/113 doc id 022508 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. nand flash devices supported by the bootrom firmware . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. spear320s uart capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. pixel widths and formats available for different display types. . . . . . . . . . . . . . . . . . . . . . . 23 table 5. headers/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 6. mclk, rtc, reset and 3.3 v comparator pins description . . . . . . . . . . . . . . . . . . . . . . . . 31 table 7. power supply pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 8. debug pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 9. smi pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 10. usb pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 11. adc pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 12. ddr pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13. pl_gpio / pl_clk pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. boot pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 15. pl_gpio/pl_clk multiplexing scheme and reset states . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 16. table shading reference for table 15 multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . 48 table 17. fsmc signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. emi signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. clcd signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 20. touchscreen signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 21. uart signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 22. can signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 23. mmc-sd/sdio controller signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 24. pwm signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 25. gpt signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 26. irda signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 27. ssp signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 28. i2c signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 29. i2s signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 30. spp signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 31. ethernet signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 32. ball sharing during debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 33. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 34. maximum power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 35. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 36. overshoot and undershoot specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 37. low voltage ttl dc input specification (3 v< v dd <3.6 v) . . . . . . . . . . . . . . . . . . . . . . . . 69 table 38. low voltage ttl dc output specification (3 v< v dd <3.6 v) . . . . . . . . . . . . . . . . . . . . . . . 69 table 39. pull-up and pull-down characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 40. mclk oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 41. mclk external user clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 42. rtc oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 43. rtc external user clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 44. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 45. driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 46. on-die termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 47. reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 48. adc pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 spear320s list of tables doc id 022508 rev 2 7/113 table 49. pl_gpio external interrupt input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 table 50. reset timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 51. can timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 52. clcd timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 53. ddr2/lpddr read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 54. ddr2/lpddr write cycle timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 55. ddr2/lpddr command timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 table 56. emi timing requirements fo r read cycle with acknowledgement on wait . . . . . . . . . . . . . 83 table 57. emi timing requirements for write cycle with acknowledgement on wait . . . . . . . . . . . . . 84 table 58. emi signals timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 59. mii tx timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 60. mii rx timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 61. mdc timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 62. rmii tx timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 63. rmii rx timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 table 64. fsmc timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 65. fsmc signals timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 66. i 2 c timing requirements in high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 67. i 2 c timing requirements in fast-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 68. i 2 c timing requirements in standard-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 69. i2s timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 70. pwm timing characterisitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 71. sd timing requirements (high-speed mode, 48 mhz). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 72. sd timing requirements (full-speed mode, 24 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 73. smi timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 74. spi master mode timing characteristics (sph = 0, spo=0) . . . . . . . . . . . . . . . . . . . . . . . . 99 table 75. spi master mode timing characteristics (sph = 0, spo=1) . . . . . . . . . . . . . . . . . . . . . . . 100 table 76. spi master mode timing characteristics (sph = 1, spo=0) . . . . . . . . . . . . . . . . . . . . . . . 101 table 77. spi master mode timing characteristics (sph = 1, spo=1) . . . . . . . . . . . . . . . . . . . . . . . 102 table 78. ssp timing characteristics (slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 79. uart transmit timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 80. uart receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 04 table 81. rs485_oe transmit and receive timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 82. lfbga289 (15 x 15 x 1.7 mm) mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 83. lfbga289 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 84. list of acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 85. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 list of figures spear320s 8/113 doc id 022508 rev 2 list of figures figure 1. spear320s architectural block diagra m. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. spear320s pin/ball map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 3. hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 4. mclk crystal connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 figure 5. rtc crystal connection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 6. power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 7. cold reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 8. warm reset release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 9. clcd waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 10. ddr2/lpddr read cycle waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 11. ddr2/lpddr write cycle waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 12. ddr2/lpddr command waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 13. emi read cycle waveform with acknowledgement on emi_wait. . . . . . . . . . . . . . . . . . . . 83 figure 14. emi write cycle waveform with acknowledgement on emi_wait . . . . . . . . . . . . . . . . . . . 83 figure 15. emi read cycle waveform without acknowledgement on emi_wait . . . . . . . . . . . . . . . . . 84 figure 16. emi write cycle waveform without acknowledgement on emi_wait . . . . . . . . . . . . . . . . . 84 figure 17. mii tx waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 18. mii rx waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 19. mdc waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 20. rmii tx waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 21. rmii rx waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 22. output command signal waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 figure 23. output address signal waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 24. in/out data address signal waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 25. output signal waveform for i 2 c signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 26. rc delay circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 27. i2s waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 28. pwm timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 figure 29. sd timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 30. smi input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 31. ssp_sck waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 32. spi master mode external timing waveform (sph= 0, spo =0 ) . . . . . . . . . . . . . . . . . . . . 98 figure 33. spi master mode external timing waveform (sph= 0, spo =1 ) . . . . . . . . . . . . . . . . . . . 100 figure 34. spi master mode external timing waveform (sph = 1, spo = 0). . . . . . . . . . . . . . . . . . . 101 figure 35. spi master mode external timing waveform (sph = 1, spo = 1). . . . . . . . . . . . . . . . . . . 102 figure 36. spp timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 37. uart transmit and receive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 38. rs485_oe transmit and receive waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 39. lfbga289 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 spear320s description doc id 022508 rev 2 9/113 1 description spear320s is a member of the spear family of embedded mpus and is optimized for industrial automation and consumer markets. the device is based on the arm926ej-s processor (up to 333 mhz), widely used in applications where the processing performance is required to be higher than the on e achievable with microcontrollers. spear320s provides an integr ated mmu (memory managemen t unit) which enables to support high-level operating systems (hlos), such as linux and windows embedded compact 7. in addition, a rich set of integrated peripherals (memory interfaces, connectivity, hmi, cryptography) allows the device to be used in a wide range of embedded applications. the spear320s architecture is based on multiple fu nctional blocks interacting through a multilayer interconnection bus matrix. the switch matrix structure allows different subsystem data flows to be executed in parallel improving the core platform efficiency. high performance master agents are directly interconnected with the memory controller reducing the memory access latency. the overall memory bandwidth assigned to each master port can be programmed and optimized through an internal efficient weighted round-robin arbitration mechanism. the spear320s device is fully backward-compatible with the previous spear320 product at both hardware and software programming levels. the extended functionality is achieved by enhanced i/o multiplexing, preserving the same pinout and ball map, as well as by a new software-definable configuration mode. description spear320s 10/113 doc id 022508 rev 2 figure 1. spear320s architec tural block diagram jtag trace etmi/f cpu subsystem lowspeedconnectivity serialflashi/f memoryinterfaces 32kb bootrom ddr2/lpddr ctrl can(2x) uart (7x) debugi/f 8kb st ti ram mmu arm9ejscore 16kb icache 16kb dcache hmifeatures ssp (3x) staticmemoryctrl externalmemory i/f rs485 i2c (3x) st a ti c ram displayctrl jpegcodec i2saudioi/f fastirda spp adc config regs businterfaces usb 2 0 host (2x) highspeedconnectivity gpio xgpio reset&clock system controller config regs (misc) vectoredinterrupt controller watchdog touchscreen i/f usb 2 . 0 host (2x) usb2.0device dmactrl cryptographic coprocessor generator timers(6x) pwm(4x) fastethernet (2x) busmatrixinterconnect opt. battery sdio/mmc rtc spear320s device functions doc id 022508 rev 2 11/113 2 device functions 2.1 cpu subsystem the core of the spear320s is an arm926ej-s reduced instruction se t computer (risc) processor. main features: supports the 32-bit arm and 16-bit thumb instruction sets, enabling the user to trade off between high performance and high code density. it also includes features for efficient execution of java byte codes. the arm cpu can be clocked at a frequency up to 333 mhz and includes both an instruction (16 kb) and a data cache (16 kb). in addition to the capability of running any real-time operating system (rtos) available for arm9 processors, the arm926ej-s subsystem also provides a memory management unit (mmu) that enables to support high-level operating systems (hlos) like linux and windows embedded compact 7. includes an embedded trace module (etm medium+) for real-time cpu activity tracing and debugging. it supports 4-bit and 8-bit normal trace mode and 4-bit demultiplexed trace mode, with normal or half-rate clock. for detailed information, please refer to the following public documents available from the arm ltd. website: cpu core: arm9ej-s, technical reference manual, revision: r1p2 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0222b/ddi0222.pdf cpu sub s y s tem: arm926ej-s, technical reference manual, revision: r0p5 http://infocenter.arm.com/help/topic/com.arm.doc.ddi0198e/ddi0198e_arm926ejs_r0p 5_trm.pdf 2.2 internal memories (bootrom/sram) spear320s integrates tw o embedded memories: 32 kb rom (bootrom), storing a factory-defined device bootstrap firmware. 8 kb static ram (sram), partly used by bootstrap firmware, but also available as general-purpose memory after system startup. the firmware in bootrom is automatically executed afte r spear320s reset and supports the following bootstrap modes: boot from serial nor flash boot from parallel nand flash boot from para llel nor flash boot from usb device port boot from uart0 boot from ethernet (mii0) device functions spear320s 12/113 doc id 022508 rev 2 the bootrom firmware selects the boot mode from the boot pin settings (see section 3.4.5: boot pin s ). a setting is also available to allow the bootrom execution to be bypassed. the first three modes support alternate ways of locating and starting the selected operating system or target custom software. such modes require a second-level boot firmware to be stored in external flash memory. a reference code for such boot loader (called ?xloader?) is provided by stmicroelectronics in source and binary format s for the spear320s evaluation boards. such code must be adapted according to the specific ddr memory components found on target customer systems. the fourth mode can be used for installing and updating the software on external flash memories through a pc-b ased software utility provided by stmicroelectronics exploiting a usb link between a pc and a target spear320s board. the sixth mode used the mii0 port and is based on two standard protocols: dhcp (to get an ip address over the network) and tftp (for receiving xloader and u-boot binary images). 2.3 multiport ddr controller (mpmc) spear320s integrates a high-performance co ntroller able to mana ge ddr2 (double data rate) and lpddr (low power ddr) external dynamic memory devices. main features: support for ddr2 up to 333 mhz (666 mt/sec) support for lpddr up to 166 mhz (333 mt/sec) support for 8-/16-bit external data bus support for up to 1 gbyte ddr2/lpddr memory address space full initialization of memo ries on controller reset 6 independent internal ports: five of them are used to access the external memory while one is reserved fo r programming the controller configuration registers programmable built-in port arbitration scheme to ensure high memory bandwidth utilization fully pipelined read and write commands self-refresh mode for power saving integrated physical layer (phy) and delay locked loops (dlls) for fine tuning of the timing parameters, maximizing the data valid windows at different frequencies 2.4 serial nor flash controller (smi) spear320s integrates a flash memory controlle r able to manage serial, spi-compatible, nor flash and eeprom external memory devices. main features: support for up to 32 mbyte external serial memory storage capacity (2 x 16 mb addressable banks by independent chip select signals) smi clock up to 50 mhz (fast read mode) or 20 mhz (normal mode), with software configurable 7-bit prescaler spear320s device functions doc id 022508 rev 2 13/113 the bootstrap requires that the external serial flash is located at bank 0 (enabled after power-on reset). during the boot phase, a sequenc e of instructions is automatically sent to bank 0. refer to the spear320s re ference manuals for more details. device functions spear320s 14/113 doc id 022508 rev 2 the bootrom firmware has been tested with the following external serial memory components: micron m25p and m45p families (spi flash) stmicroelectronics m95 family (spi eeprom), except for m95040, m95020 and m95010 atmel at25f family (spi flash) ymc y25f family (spi flash) microchip/sst sst25lf family (spi flash) 2.5 parallel nand flash controller (fsmc) spear320s integrates a flexible static memory controller able to manage external parallel nand flash memories. main features: 8-/16-bit external data bus; 16-bit only supported when mode 3 (expanded automation mode) chip configuration is selected by software. support for up to 4 memory banks independent timing configuration and chip select signal for each memory bank fully programmable timings: ? wait states (up to 31) ? bus turnaround cycles (up to 15) ? output enable and write enable delays (up to 15) external asynchronous wait control internal ahb bus burst transfer support to reduce flash memory access time the bootrom firmware directly supports the external nand flash components shown in ta bl e 2 . table 2. nand flash devices supp orted by the bootrom firmware part number vendor density capacity bus width page size k9f1208v0a samsung 64 mb 8 mb x8 512 + 16 bytes nand128w3a28n6 micron 128 mb 16 mb x8 512 + 16 bytes nand256w3a2bn6 micron 256 mb 32 mb x8 512 + 16 bytes km29u256 samsung 256 mb 32 mb x8 512 + 16 bytes nand512w3a2c2a6 micron 512 mb 64 mb x8 512 + 16 bytes nand01gw3b2bn6 micron 1 gb 128 mb x8 2048 + 64 bytes nand01gw4b2an6 micron 1 gb 128 mb x16 1024 words + 32 bytes k9f1g16u0m samsung 1 gb 128 mb x16 1024 words + 32 bytes nand01gr3b micron 1 gb 128 mb x8 2048 + 64 bytes nand02gw3b2cn6 micron 2 gb 256 mb x8 2048 + 64 bytes spear320s device functions doc id 022508 rev 2 15/113 2.6 external memory interface (emi) spear320s integrates an additional external me mory interface that can be used to manage external parallel nor flash memories as well as fpga devices. this interface is available only when mode 3 (expanded automation mode) chip configuration is selected by software. main features: 24-bit address bus 16-bit data bus 4 chip select signals support for single asynchronous transfers support for peripherals using byte lane procedure the external flash component must be in read mode at reset. usually, this is true for most parallel nor devices. 2.7 usb 2.0 host ports (uhc) spear320s provides two usb 2.0 host ports with integrated phys. main features: each port can be independently configured for high-speed mode (usb 2.0, up to 480 mbps); in this case, the corresponding controller is programmed according to standard ehci specifications. each port can be independently configured for full-speed mode (usb 1.1, up to 12 mbps) or low-speed mode (usb 1.1, up to 1.5 mbps); in this case, the corresponding controller is programmed according to standard ohci specifications. internal 2 kb fifo queues internal dma support dedicated output control signals to manage external power switches dedicated input signals to sense any over-current condition detected by external power switches nand02gw3a micron 2 gb 256 mb x8 2048 + 64 bytes k9f2g08v0a samsung 2 gb 256 mb x8 512 + 16 bytes nand04gw3b2bn6 micron 4 gb 512 mb x8 2048 + 64 bytes k9f4g08v0a samsung 4 gb 512 mb x8 512 + 16 bytes nand08gw3b2cn6 micron 8 gb 1 gb x8 2048 + 64 bytes k9k8g08v0a samsung 8 gb 1 gb x8 512 + 16 bytes k9f8g08v0m samsung 8 gb 1 gb x8 512 + 16 bytes table 2. nand flash devices supported by the boot rom firmware (continued) part number vendor density capacity bus width page size device functions spear320s 16/113 doc id 022508 rev 2 2.8 usb 2.0 device port (udc) spear320s provides a usb 2.0 devi ce port with integrated phy. main features: support for all standard modes: ? high-speed mode (usb 2.0, up to 480 mbps) ? full-speed mode (usb 1.1, up to 12 mbps) ? low-speed mode (usb 1.1, up to 1.5 mbps) up to 16 physical endpoints, configurable as different logical endpoints internal 4 kb fifo queue (shared among all the endpoints) dma mode, with descriptor-based structures in application memory slave-only mode support for 8-, 16- and 32-bit wide data transactions on the internal bus support for usb plug detection (upd) 2.9 fast ethernet ports (mii/rmii) spear320s features three multiplexed ether net macs, supporting up to two ports concurrently. the three controllers are named: mii0 rmii0 mii1/rmii1 2.9.1 mii0 ethernet controller main features: media independent interface (mii) to an ex ternal phy as defined in the ieee 802.3u specification support for 10 and 100 mbps data transfer rates support for both full-duplex and half-duplex (csma/cd protocol) operating modes integrated fifo queues (4 kb rx, 2 kb tx) native dma with single-channel transmit and receive engines, providing 32-/64-/128-bit data transfers; dma provides ring-buffer or linked-list descriptor options. programmable ethernet frame length to support both standard and jumbo frames (with size up to 16 kb) flexible address filtering modes statistics counter registers for rmon/mib support for 802.1q vlan tagging wake-on-lan support automatic padding and crc generation on transmitted frames spear320s device functions doc id 022508 rev 2 17/113 2.9.2 rmii0 and mii1/rmii 1 ethernet controllers these functional blocks extend ethernet capability by covering the media independent interface (mii) and reduced media independent interface (rmii) standards. they can be used in two ways: as a single additional mac controller with media independent interface (mii1) as two mac controllers with reduced media independent interface (rmii0, rmii1) in rmii configuration , each controller has an independent set of data and control lines. the reference clock (50 mhz) is shared by the controllers. main features: compatible with ieee standard 802.3 unh tested 10 and 100 mbit/s operation full and half duplex operation statistics counter registers for rmon/mib automatic pad and crc generation on transmitted frames automatic discard of frames received with errors address checking logic supports up to four specific 48-bit addresses supports promiscuous mode where all valid received frames are copied to memory hash matching of unicast and multicast destination addresses external address matching of received frames supports serial network interface operation half-duplex flow control by forc ing collisions on incoming frames full-duplex flow control with recognition of incoming pause frames and hardware generation of transmitted pause frames support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames multiple buffers per receive and transmit frame jumbo frames of up to 10240 bytes supported 2.10 mmc-sd card/sdio controller the mmc-sd card /sdio controller conforms to the sd host controller standard specification, version 2.0. it handles sd/sdio protocol at transmission level by packing data, adding cyclic redundancy check (crc) and start/end bit as well as checking for transaction format correctness. the controller is designed to work with i/o cards, read-only cards and read/write cards, and can operate either in sd mode (1-bit, 4-bit, 8-bit) or in spi mode. device functions spear320s 18/113 doc id 022508 rev 2 the interface is compliant to the following standards: sd host controller standard specification, version 2.0 sdio card specification, version 2.0 sd memory card specific ation draft, version 2.0 sd memory card security specification, version 1.01 mmc specification, version 3.31 and 4.2 main features: up to 100 mbps data rate using 4 parallel data lines (sd4 bit mode) up to 416 mbps data rate using 8-bit parallel data lines (sd8 bit mode) dma-based and non-dma modes of operation support for mmc plus and mmc mobile card detection (insertion / removal) card password protection host clock rate variable between 0 and 48 mhz multimedia card interrupt mode cyclic redundancy check: crc7 (c ommand) and crc16 (data integrity) error correction code (ecc) support for mmc4.2 cards supports for read wait control and suspend/resume fifo overrun and under-run handling by stopping sd clock 2.11 can 2.0 ports spear320s provides two independent can (contr oller area network) bus ports, typically used in automotive, industrial and medical applications. for the connection to the physical layer, an additional transceiver per port is required. for communication on a can network, the controller enables to configure individual message objects. the message objects and identifier masks for acceptance filtering of received messages are stored in an integrated message ram. all functions concerning the handling of messages are implemented by a message handler. those functions are the acceptance filtering, the transfer of messages between the can core and the message ram, the handling of transmission requests as well as the generation of interrupts. main features: support for can protocol, version 2.0 part a and b transfer rate up to 1 mbps internal ram storage for up to 16 message objects (16 x 136 bytes memory) identifier mask per message object maskable interrupts programmable loop-back mode for self-test operation disabled automatic retransmission mode for time triggered can applications spear320s device functions doc id 022508 rev 2 19/113 2.12 asynchronous serial ports (uart) the spear320s has 7 uart ports. the actual number of concurrently exploitable ports depends on the selected chip operating mode. the different capabilities of each port are summarized in ta b l e 3 below. main features: programmable baud rate generator transmit fifo queue (8-bit data, 16 entries) and receive fifo queue (12-bit data/status, 16 entries) with disabling option (1-byte buffer depth) supports for dma operation hardware flow control (rts,cts) for some ports and configurations modem control signals (dcd, dsr, dts, ri) for some ports and configurations fully programmable serial inte rface with following parameters: ? data bits: 5, 6, 7 or 8 ? parity: even, odd, stick or none (generation and detection) ? stop bits: 1 or 2 ? line break handling (generation and detection) flexible interrupt handing and masking table 3. spear320s uart capabilities port speed hardware flow control modem signals uart0 up to 3 mbps yes yes (as alternate function) uart1 up to 7 mbps yes (except for mode 1 and 2) yes (except for mode 1 and 2) uart2 - 6 up to 7 mbps no no device functions spear320s 20/113 doc id 022508 rev 2 2.13 i2c bus ports (i2c) the spear320s provides three independent i2c bus ports. ea ch port can be configured as i2c bus master or slave. main features: compliant to the i2c bu s specification (philips) support for the 3 standard speeds: ? standard (100 kbps) ? fast (400 kbps) ? high-speed support for direct memory access (dma) clock synchronization support for slave operation in multimaster environment 7-bit or 10-bit addressing 7-bit or 10-bit combined format transfers slave bulk transfer mode transmit and receive buffers interrupt or polled-mode operation handling of bit and byte waiting at all bus speeds digital filter for the re ceived sda and scl lines filtering out of legacy cbus addresses 2.14 synchronous serial ports (ssp) spear320s provides three ind ependent synchr onous serial ports. each port can be configured as master or slave. main features: support for the following protocols: ? spi (motorola) ? microwire (national semiconductor) ? ssi (texas instruments) programmable parameters: ? clock bit rate and prescale ? data frame size (from 4 to 16 bits) separate transmit and receive fifo queues (8 x 16-bit entries) independent masking of transmit fifo, receive fifo, and receive overrun interrupts internal loopback test mode available dma interface spear320s device functions doc id 022508 rev 2 21/113 2.15 rs485 port (rs485) spear320s provides an additi onal uart port specialized for the rs485 standard. main features: transmit fifo queue (8-bit data, 16 entries) and receive fifo queue (12-bit data/status, 16 entries) with disabling option (1-byte buffer depth) speed up to 7 mbps 2.16 fast infrared port (irda) spear320s provides an infrared in terface compliant to the irda (infrared data association) standard specification. an external infrared transceiver is assumed. the fast irda controller performs the modulation and demodulation of the infrared signals as well as the wrapping of irda link access protocol (irlap) frames. main features: support for the following standards: ? irda serial infrared physical layer specification (irphy), version 1.3 ? irda link access protocol (irlap), version 1.1 support for the following modes and baud rates: ? serial infrared (sir): 9.6 kbps, 19.2 kbps, 38.4 kbps, 57.6 kbps, 115.2 kbps ? medium infrared (mir): 576 kbps, 1152 kbps ? fast infrared (fir): 4 mbps support for half-duplex infrared frame transmission and reception interface compliant to all irda transceivers with configurable polarity of tx and rx signals integrated crc algorithm: 16-bit (sir, mir), 32-bit (fir) automatic generation of preamble, start and stop flags rzi (return-to-zero inverted) modulation/demodulation scheme for sir and mir modes 4ppm (4-pulse position modulation) modulation/demodulation scheme for fir mode synchronization by dpll in fir mode payload data transfer controllable by either cpu or dma controller two clock domains: ? dedicated clock (irda_clk signal) for accurate signal generation (48 mhz) ? independent and variable clock for the bus interface (13 mhz) 2.17 legacy ieee 1284 parallel port (spp) spear320s provides a parallel port (slave mode only) compliant to the legacy ieee 1284 standard. main features: unidirectional 8-bit data transfer fr om external host to spear320s slave additional 9th bit for parity/data/command maskable interrupts for data, device reset, auto line feed device functions spear320s 22/113 doc id 022508 rev 2 2.18 a/d converter (adc) spear320s provides an integrated analog-to -digital converter. main features: successive approximatio n conversion method 8 x analog input channels, ranging from 0 to 2.5 v 10-bit resolution sampling rate up to 1 msamples/s support for 13.5-bit resolution at 8 ksamples/s by oversampling and accumulation inl 1 lsb, dnl 1 lsb programmable conversion speed (minimum conversion time is 1 s) programmable averaging of multiple values from 1 (no averaging) up to 128 programmable auto scan for all the 8 channels 2.19 general purpose i/os (gpio/xgpio) up to 102 gpios are available in spear320s when some embedded ips are not needed in the customer application (see section 3.4: shared io pin s (pl_gpio s ) ). spear320s provides two mechanisms: a basic gpio module (called ?basgpio?): this functional block provides 6 pins, each one programmable by software with the following features: ? programmable direction: input (default at reset) or output ? progammable edge-sensitive and level-sensitive interrupt triggering extended gpios (xgpio): this capability allows any pl_gpi o pin to be configured and used as an alternative to the corresponding predefined signal purpose. xgpios have a different register programming model from basic gpios with the following features: ? programmable direction: input or output ? progammable edge-sensitive interrupt triggering spear320s device functions doc id 022508 rev 2 23/113 2.20 lcd display controller (clcd) spear320s has an integrated disp lay controller able to directly interface a variety of color and monochrome lcd panels. main features: programmable resolution up to 1024 x 768 (xga) programmable timing parameters support for tft (thin film transistor) color displays supports for stn (super twisted nematic) disp lays (single and dual panel) with 4- or 8- bit interfaces ac bias signal for stn and data enable signal for tft panels gray scaling algorithm the set of supported pixel widths and formats for each display type is shown in ta b l e 4 . 2.21 touchscreen interface (touchscreen) spear320s provides a to ggling output signal (touchs creen_x) that can be connected to an external touchscreen panel. this interface operates in combination with the a/d converter (adc). two coordinates can be read by software from the adc: one at the end of the high period and one at the end of the low period of touchscreen_x signal. table 4. pixel widths and formats available for different display types display 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 24 bpp color tft palette of 2 colors over 64k palette of 4 colors over 64k palette of 16 colors over 64k palette of 256 colors over 64k rgb 5:5:5 + intensity (64k colors) rgb 8:8:8 (16m colors) color stn palette of 2 colors over 3375 palette of 4 colors over 3375 palette of 16 colors over 3375 palette of 256 colors over 3375 rgb 4:4:4 (4096 colors) - mono stn palette of 2 gray levels over 15 palette of 4 gray levels over 15 palette of 16 gray levels over 15 palette of 256 colors over 3375 -- device functions spear320s 24/113 doc id 022508 rev 2 2.22 jpeg codec a ccelerator (jpgc) spear320s provides an integrat ed hardware accelerator for decoding and encoding standard jpeg images. jpeg data streams to be decoded must be compliant with the interchange format syntax specified in the iso/iec 10918-1. the jfif image file format is also supported through header processing. the output format for decoding (and input format for encoding) is a mcu stream, not a conventional bitmap format like rgb. displayin g a decoded jpeg still picture would require further steps and algorithms like color space conversion and scaling. main features: compliance with the baseline jpeg standard (iso/iec 10918-1) single-clock per pixel encoding/decoding support for up to four channels of component color 8-bit/channel pixel depths programmable quantization tables (up to four) programmable huffman tables (two ac and two dc) programmable minimum coded unit (mcu) configurable jpeg header processing support for restart marker insertion use of two dma channels and two 8 x 32-bit fifos (local to the jpeg) for efficient transferring and buffering of encoded/decoded data from/to the codec core. 2.23 digital audio port (i2s) the spear320s integrates a digital audio po rt compliant to sta ndard i2s (philips) specifications. main features: i2s master mode stereo (2.0) playback and recording support for standard sampling rates (8, 16, 32, 44.1, 48, 96, 192 khz); the clock input is 24 mhz, so the rate precision depends on the chosen rate and divider. support of a range of audio samples: 12 / 16 / 20 / 24/ 32 bits programmable thresholds for internal fifo queues capability of using dma transfer 2.24 cryptographic co-processor (c3) spear320s provides an embedded cryptographi c co-processor (c3). c3 is a high- performance instruction-driven dma-based engine that can be used to accelerate the processing of security algorithms. after its initial configuration by the main cpu, it runs in a completely autonomous way (dma data in, data processing, dma data out), until the completion of all the requested operations. c3 firmware is fetched from system memory. spear320s device functions doc id 022508 rev 2 25/113 main features: supported cryptographic algorithms: ? advanced encryption sta ndard (aes) cipher in ecb, cbc, ctr modes ? data encryption standard (des) cipher in ecb and cbc modes ? sha-1, hmac-sha-1, md5, hmac-md5 digests hardware chaining of cryptographic stages for optimized data flow when multiple algorithms are required to process the same set of data (for example, encryption and hashing on the fly) 2.25 system cont roller (sysctr) the system controller provides an interface for controlling the operation of the overall system. main features: power saving system mode control crystal oscillator and pll control configuration of system response to interrupts reset status capture and soft reset generation watchdog and timer module clock enable using three mode control bits, the system controller switches the spear320s to any of the four different modes: doze, sleep, slow and normal. sleep mode : in this mode, the system clocks, hc lk and clk, are disabled and the system controller clock, sclk, is driven by a low-speed oscillator (nominally 32768 hz). when either a fiq or an irq interrupt is generated (through the vic), the system enters doze mode. additionally, the operating mode setting in the system control register automatically changes from sleep to doze. doze mode : in this mode, the system clocks, hclk and clk, and the system controller clock are driven by a crystal osc illator (24 mhz) or a lo w-frequency oscillator (32 khz). the system controller moves into sleep mode from doze mode only when none of the mode control bits are set and the processor is in wait-for-interrupt state. if slow mode or normal mode is required, the system moves into the xtal control transition state to initialize the crystal oscillator. slow mode : during this mode, both the system clocks and the system controller clock are driven by the crystal oscillator. if norm al mode is selected, th e system goes into the ?pll control? transition state. if neither the slow nor the normal mode control bits are set, the system goes into the ?switch from xtal? transition state. normal mode : in normal mode, both the system clocks and the system controller clock are driven by the pll output. if the normal mode control bit is not set, then the system goes into the ?switch from pll? transition state. device functions spear320s 26/113 doc id 022508 rev 2 2.25.1 reset and clock generator the reset and clock generator is a fully programmable block that generates all the clocks necessary to the chip. the default operating clock frequencies are: clock @ 333 mhz for the cpu. clock @ 166 mhz for ahb bus and ahb peripherals. clock @ 83 mhz for, apb bus and apb peripherals. clock @ 333 mhz for ddr memory interface. the default values give the maximum allowed clock frequencies. the clock frequencies are fully programmable through dedicated registers. the reset and clock generator consists of 2 main parts: multiclock generator block 3 internal plls the multiclock generator block receives a reference signal (which is usually delivered by the pll) and generates all clocks for spear320s ips according to dedicated programmable registers. each pll uses an o scillator input of 24 mhz to generate a clock signal at a frequency corresponding at the highest of the group. this is the reference signal used by the multiclock generator block to obtain all the other requested clocks for the group. its main feature is the electromagnetic in terference reduct ion capability. you can set up pll1 and pll2 in order to modulate the vco with a triangular wave. the resulting signal has a spectrum (and power) spread over a small programmable range of frequencies centered on f0 (the vco frequ ency), obtaining minimum electromagnetic emissions. this method replaces all the other traditional methods of emi reduction, such as filtering, ferrite beads, chokes, adding power layers and ground planes to pcbs, metal shielding and so on. this of fers important cost savings. 2.26 vectored interrupt controller (vic) spear320s integrates a vectored interrupt controller which provi des a software interface to the interrupt system. in any system with an interrupt controller, the software has to determine the source that requests service and where its service routine is loaded. the vic inside spear320s does both of these in hardware. it supplies the starting address, or vector address, of the service routine corresponding to the highest priority requesting interrupt source. as in any arm9-based system, two levels of interrupts are available: fast interrupt requests (fiq), for fast, low latency interrupt handling normal interrupt requests (irq), for more general interrupts the interrupt inputs must be level sensitive, active high, and held asserted until the interrupt service routine clears the interrupt. edge-triggered interrupts are not compatible. the interrupt inputs do not have to be synchronous to hclk. the vic does not handle interrupt sources with transient behavior. for example, an interrupt is asserted and then de- asserted before software can clear the interrupt source. in this case, the cpu acknowledges the interrupt and obtains the vectored address for the interrupt from the vic, assuming that no other interrupt has occurred to overwrite the vectored address. however, when a spear320s device functions doc id 022508 rev 2 27/113 transient interrupt occurs, the priority logic of the vic is not set, and lower priority interrupts can interrupt the transient interrupt service routine, assuming interrupt nesting is permitted. there are 32 interrupt lines. the vic uses a bit position for each different interrupt source. the software can control each request line to generate software interrupts. there are 16 vectored interrupts. these interrupts can only generate an irq interrupt. the vectored and non-vectored irq interrupts provide an address for an interrupt service routine (isr). the fiq interrupt has the highest priority, followed by interrupt vector 0 to interrupt vector 15. non-vectored irq interrupts have the lowest priority. the specific interrup t map for the spear320s device is documented in the companion reference manuals. 2.27 watchdog timer (wdt) the arm watchdog module consists of a 32-bit down counter with a programmable time-out interval that has the capability to generate an interrupt and a reset signal on timing out. the watchdog module is intended to be used to apply a reset to a system in the event of a software failure. 2.28 real-time clock (rtc) the real-time clock provides an 1-second resolution clock. this keeps time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. main features: time-of-day clock in 24 hour mode calendar alarm capability isolation mode, allowing rtc to work even if power is not supplied to the rest of the device. 2.29 dma controller (dmac) spear320s provides one dma controller. main features: able to service up to 8 independent dma channels for serial data transfers between single source and destination (for instance, memory-to-memory, memory-to-peripheral, peripheral to- memory, and peripheral-to-peripheral). each dma channel can support a unidirectional transfer, with internal four-word fifo per channel. device functions spear320s 28/113 doc id 022508 rev 2 2.30 general purpose timers (gpt) spear320s provides 6 ge neral purpose timers. main features: each timer provides a programmable 16-bit counter and a dedicated prescaler able to perform a clock division by 1 up to 256 (different input frequencies can be chosen through configuration registers, in the range from 3.96 hz to 48 mhz) operating modes: ? auto-reload mode: when a software-defined value is reached, an interrupt is triggered and the counter automatically restarts from zero ? single-shot mode: when a software-defined value is reached, an interrupt is triggered, the counter is stopped and the timer is disabled capture capability (only for 4 timers) 2.31 pulse width modulators (pwm) spear320s integrates 4 pwm (pulse wid th modulation) signal generators. main features: prescaler to define the input clock frequency to each timer programmable duty cycle from 0% to 100% programmable pulse length spear320s pin description doc id 022508 rev 2 29/113 3 pin description this chapter provides a full description of the ball characteristics and the signal multiplexing of spear320s device. section 3.1 shows the pin/ball map of spear320s. section 3.2 lists the required external components to connect. section 3.3 describes some dedicated pins, such as: clock, re s et and 3v3 comparator pin s power s upply pin s debug pin s non-multiplexed pin s section 3.4 provides a complete description of the shared io pins (pl_gpios) and their configuration modes, as well as detailed informat ion on all multiplexed signals, grouped by ip. section 3.5 explains the available debug modes. the following table defines the table headers and abbreviations used in this chapter. table 5. headers/abbreviations header description abbreviations group grouping of signals of the sa me type/functional block. ? signal name name of signal multiplexed on each ball. ? direction (dir.) indicates the direction of the signal. i= input o= output io= input/output pl_gpio_# /ball pl_gpio and ball number associated with each signal on the package. ? configuration mode indicates the available configuration mode among the following ones: ? mode 1 ? mode 2 ? mode 3 ? mode 4 ? alternate function ? extended mode see section 3.4.2 for the description of each mode. ? pin type pad type information pu= pull up pd= pull down gnd= ground value indicates the electrical value on the ball. ? spear320s pin description doc id 022508 rev 2 30/113 3.1 pin/ball map figure 2. spear320s pin/ball map 12 3 4567 8 9 1011121 3 14 15 16 17 a pl_gpio_1 3 pl_gpio_14 pl_gpio_1 9 pl_gpio_2 3 pl_gpio_26 pl_gpio_2 8 pl_gpio_2 9 pl_gpio_ 38 pl_gpio_ 39 pl_gpio_44 pl_gpio_46 pl_gpio_50 pl_gpio_55 pl_gpio_60 pl_gpio_62 pl_gpio_6 9 pl_gpio_7 3 b pl_gpio_6 pl_gpio_ 9 pl_gpio_15 pl_gpio_20 pl_gpio_24 pl_gpio_27 pl_gpio_ 3 0 pl_gpio_ 3 7 pl_gpio_40 pl_gpio_45 pl_gpio_4 8 pl_gpio_52 pl_gpio_5 9 pl_gpio_65 pl_gpio_6 8 pl_gpio_72 pl_gpio_77 c pl_gpio_4 pl_gpio_ 8 pl_gpio_10 pl_gpio_17 pl_gpio_21 pl_gpio_25 pl_gpio_ 3 1pl_gpio_ 3 6 pl_gpio_41 pl_gpio_47 pl_gpio_4 9 pl_gpio_56 pl_gpio_6 3 pl_gpio_67 pl_gpio_70 pl_gpio_74 pl_gpio_ 8 1 d pl_gpio_ 3 pl_gpio_5 pl_gpio_7 pl_gpio_12 pl_gpio_1 8 pl_gpio_22 pl_gpio_ 3 2 pl_gpio_ 3 5 pl_gpio_42 pl_gpio_51 pl_gpio_5 3 pl_gpio_5 8 pl_gpio_64 pl_gpio_71 pl_gpio_7 8 pl_gpio_ 8 0pl_gpio_ 8 4 e rtc_xo rtc_xi pl_gpio_1 pl_gpio_2 pl_gpio_11 pl_gpio_16 pl_gpio_ 33 pl_gpio_ 3 4 pl_gpio_4 3 pl_gpio_54 pl_gpio_57 pl_gpio_61 pl_gpio_66 pl_gpio_75 pl_gpio_ 8 2pl_gpio_ 83 pl_gpio_ 8 6 f rtc_vdd1v5 rtc_gnd pl_gpio_0 digital_ gndbg comp digit a l_vdde 3 v 3 digit a l_vdde 3 v 3 digit a l_vdde 3 v 3 vdd vdd digit a l_vdde 3 v 3 digit a l_vdde 3 v 3 digit a l_vdde 3 v 3 pl_gpio_76 pl_gpio_7 9 pl_gpio_ 8 5pl_gpio_ 88 pl_gpio_ 89 g dith_pll_v ss _ a n a dith_pll_vdd _ a n a u s b_device _ vbu s digital_ rext digit a l_vdde 3 v 3 gnd gnd gnd gnd gnd gnd vdd pl_gpio_ 8 7 pl_gpio_ 9 0 pl_gpio_ 9 1 pl_gpio_ 9 2 pl_gpio_ 93 h u s b_ho s t1_ dp u s b_ho s t1_ dm u s b_ho s t1_ vbu s u s b_ho s t0_ overcur vdd gnd gnd gnd gnd gnd gnd vdd pl_gpio_ 9 4pl_gpio_ 9 5pl_gpio_ 9 6pl_gpio_ 9 7pl_clk4 j u s b_ho s t1_ vdd 3 v 3 gnd u s b_ho s t0_ vbu s u s b_ho s t1_ overcur vdd gnd gnd gnd gnd gnd gnd digit a l_vdde 3 v 3 ddr2_en boot_ s el te s t_4 pl_clk 3 pl_clk2 k u s b_ho s t0_ dp u s b_ho s t0_ dm u s b_ho s t1_ vdd2v5 u s b_ho s t0_ vdd 3 v 3 u s b_txr tune gnd gnd gnd gnd gnd gnd digit a l_vdde 3 v 3 te s t_ 3 te s t_2 te s t_1 te s t_0 pl_clk1 l gnd u s b_ho s t0_ vdd2v5 gnd u s b_analo g te s t gnd gnd gnd gnd gnd gnd vdd digit a l_vdde 3 v 3 tm s tdi tdo ntr s ttck m u s b_device _ dp u s b_device _ dm u s b_ho s t1_ ho s t0_ device_ dvdd1v2 dith_vdd2v5 ddr_vdde1v 8 vdd vdd gnd gnd gnd vdd digit a l_vdde 3 v 3 s mi_datain s mi_dataout s mi_c s _0 s mi_c s _1 mre s et n u s b_device _vdd2v5 gnd u s b_device _vdd 3 v 3 dith_v ss 2v5 ddr_vdde1v 8 ddr_vdde1v 8 ddr_vdde1v 8 ddr_vdde1v 8 ddr_vdde1v 8 ddr_vdde1v 8 ddr_vdde1v 8 adc_ a gnd adc_ a vdd adc_vrefn ain_1 ain_0 s mi_clk p mclk_xi mclk_xo mclk_gnd ddr_mem_ comp2v5_ rext ddr_mem_ addr_ 9 ddr_mem_ addr_10 ddr_mem_ ba_0 ddr_mem_ ba_1 ddr_mem_ c s _0 ddr_mem_ vref ddr_mem_ dq_0 ddr_mem_ dq_6 ddr_mem_ dq_7 adc_vrefp ain_4 ain_ 3 ain_2 r mclk_vdd mclk_ vdd2v5 mclk_ gnd s ub ddr_mem_ comp2v5_ gndbgcom p ddr_mem_ addr_ 8 ddr_mem_ addr_11 ddr_mem_ addr_14 ddr_mem_ ba_2 ddr_mem_ c s _1 ddr_mem_ gate_open _0 ddr_mem_ dq_1 ddr_mem_ dq_5 ddr_mem_ dq_15 ddr_mem_ gate_open _1 ain_7 ain_6 ain_5 t ddr_mem_ addr_1 ddr_mem_ addr_0 ddr_mem_ odt_0 ddr_mem_ odt_1 ddr_mem_ addr_7 ddr_mem_ addr_12 ddr_mem_ we ddr_mem_ ca s ddr_mem_ clkp nddr_mem_ dq s _0 ddr_mem_ dq_2 ddr_mem_ dq_4 ddr_mem_ dq_14 ddr_mem_ dm_1 nddr_mem_ dq s _1 ddr_mem_ dq_ 9 ddr_mem_ dq_ 8 u ddr_mem_ addr_2 ddr_mem_ addr_ 3 ddr_mem_ addr_4 ddr_mem_ addr_5 ddr_mem_ addr_6 ddr_mem_ addr_1 3 ddr_mem_ clken ddr_mem_ ra s ddr_mem_ clkn ddr_mem_ dq s _0 ddr_mem_ dq_ 3 ddr_mem_ dm_0 ddr_mem_ dq_1 3 ddr_mem_ dq_12 ddr_mem_ dq s _1 ddr_mem_ dq_11 ddr_mem_ dq_10 spear320s pin description doc id 022508 rev 2 31/113 3.2 required external components some pads require the use of an external component. please follow the instructions below to ensure the proper functioning of the device: 1. ddr_comp_1v8: place an external 121 k resistor between ball p4 and ball r4 2. usb_tx_rtune: connect an external 43.2 pull-down resistor to ball k5 3. digital_rext: place an external 121 k resistor between ball g4 and ball f4 4. dith_vdd_2v5: add a ferrite bead to ball m4 3.3 dedicated pins description 3.3.1 clock, reset and 3v3 comparator pins table 6. mclk, rtc, reset and 3.3 v comparator pins description group signal name description dir. pin type ball master clock (mclk) mclk_xi 24 mhz (typical) crystal in i oscillator 2.5 v capable p1 mclk_xo 24 mhz (typical) crystal out o p2 real-time clock (rtc) rtc_xi 32 khz crystal in i oscillator 1v5 capable e2 rtc_xo 32 khz crystal out o e1 reset mreset main reset i ttl schmitt trigger input buffer, 3.3 v tolerant m17 3.3 v comparator digital_rext configuration o analog, 3.3 v capable g4 digital_gndbgcomp power power power f4 pin description spear320s 32/113 doc id 022508 rev 2 3.3.2 power supply pins note: all the vdd 2v5 power s upplie s are analog vdd. table 7. power supply pins description group signal name value ball digital ground gnd 0 v g6 g7 g8 g9 g10 g11 h6 h7 h8 h9 h10 h11 j6 j7 j8 j9 j10 j11 k6 k7 k8 k9 k10 k11 l6 l7 l8 l9 l10 m8 m9 m10 usb_host1_host0_ device_dvss l5 analog ground rtc_gnd 0 v f2 dith_pll_vss_ana g1 usb_host1_vssa j2 usb_host0_vssa l1 usb_common_vssac l3 usb_device_vssa n2 dith_vss2v5 n4 mclk_gnd p3 mclk_gndsub r3 adc_agnd n12 io digital_vdde3v3 3.3 v f5 f6 f7 f10 f11 f12 g5 j12 k12 l12 m12 core vdd 1.2 v f8 f9 g12 h5 h12 j5 l11 m6 m7 m11 usb host0 phy usb_host0_vdd2v5 2.5 v l2 usb_host0_vdd3v3 3.3 v k4 usb host1 phy usb_host1_vdd2v5 2.5 v k3 usb_host1_vdd3v3 3.3 v j1 usb device phy usb_device_vdd2v5 2.5 v n1 usb_device_vdd3v3 3.3 v n3 usb_host1_host0_devi ce_dvdd1v2 1.2 v m3 osci (mclk) mclk_vdd 1.2 v r1 mclk_vdd2v5 2.5 v r2 pll1 dith_pll_vdd_ana 2.5 v g2 pll2 dith_vdd_2v5 2.5 v m4 ddr io ddr_vdde1v8 1.8 v m5 n5 n6 n7 n8 n9 n10 n11 adc adc_avdd 2.5 v n13 osci (rtc) rtc_vdd1v5 1.5 v f1 spear320s pin description doc id 022508 rev 2 33/113 3.3.3 debug pins 3.3.4 non-multiplexed pins table 8. debug pins description signal name description dir. pin type ball test_0 debug mode configuration ports. see also section table 32.: ball s haring during debug . i ttl input buffer, 3.3 v tolerant, pd k16 test_1 k15 test_2 k14 test_3 k13 test_4 j15 boot_sel reserved, to be fixed at high level j14 ntrst test reset input i ttl schmitt trigger input buffer, 3.3 v tolerant, pu l16 tdo test data output o ttl output buffer, 3.3 v capable 4 ma l15 tck test clock i ttl schmitt trigger input buffer, 3.3 v tolerant, pu l17 tdi test data input i l14 tms test mode select i l13 table 9. smi pins description signal name description dir. pin type ball smi_datain serial flash input data i ttl input buffer 3.3 v tolerant, pu m13 smi_dataout serial flash output data o ttl output buffer 3.3 v capable 4 ma m14 smi_clk serial flash clock io n17 smi_cs_0 serial flash chip select o m15 smi_cs_1 m16 pin description spear320s 34/113 doc id 022508 rev 2 table 10. usb pins description group signal name description dir. pin type ball usb device usb_device_dp usb device d+ io bidirectional analog buffer 5 v tolerant m1 usb_device_dm usb device d- m2 usb_device_vbus usb device vbus i ttl input buffer 3.3 v tolerant, pd g3 usb host usb_host1_dp usb host1 d+ io bidirectional analog buffer 5 v tolerant h1 usb_host1_dm usb host1 d- h2 usb_host1_vbus usb host1 vbus o ttl output buffer 3.3 v capable, 4 ma h3 usb_host1_overcur usb host1 over-current i ttl input buffer 3.3 v tolerant, pd j4 usb_host0_dp usb host0 d+ io bidirectional analog buffer 5 v tolerant k1 usb_host0_dm usb host0 d- k2 usb_host0_vbus usb host0 vbus o ttl output buffer 3.3 v capable, 4 ma j3 usb_host0_overcur usb host0 over-current i ttl input buffer 3.3 v tolerant, pd h4 usb usb_txrtune reference resistor o analog k5 usb_analog_test analog test output o analog l4 table 11. adc pins description signal name description dir. pin type ball ain_0 adc analog input channel i analog buffer 2.5 v tolerant n16 ain_1 n15 ain_2 p17 ain_3 p16 ain_4 p15 ain_5 r17 ain_6 r16 ain_7 r15 adc_vrefn adc negative voltage reference n14 adc_vrefp adc positive voltage reference p14 spear320s pin description doc id 022508 rev 2 35/113 table 12. ddr pins description signal name description dir. pin type ball ddr_mem_add_0 address line o sstl_2/sstl_18 t2 ddr_mem_add_1 t1 ddr_mem_add_2 u1 ddr_mem_add_3 u2 ddr_mem_add_4 u3 ddr_mem_add_5 u4 ddr_mem_add_6 u5 ddr_mem_add_7 t5 ddr_mem_add_8 r5 ddr_mem_add_9 p5 ddr_mem_add_10 p6 ddr_mem_add_11 r6 ddr_mem_add_12 t6 ddr_mem_add_13 u6 ddr_mem_add_14 r7 ddr_mem_ba_0 bank select o p7 ddr_mem_ba_1 p8 ddr_mem_ba_2 r8 ddr_mem_ras row address strobe o u8 ddr_mem_cas column address strobe o t8 ddr_mem_we write enable o t7 ddr_mem_clken clock enable o u7 ddr_mem_clkp differential clock o differential sstl_2/ sstl_18 t9 ddr_mem_clkn u9 ddr_mem_cs_0 chip select o sstl_2/ sstl_18 p9 ddr_mem_cs_1 r9 ddr_mem_odt_0 on-die termination enable lines io t3 ddr_mem_odt_1 t4 pin description spear320s 36/113 doc id 022508 rev 2 ddr_mem_dq_0 data lines (lower byte) io sstl_2/ sstl_18 p11 ddr_mem_dq_1 r11 ddr_mem_dq_2 t11 ddr_mem_dq_3 u11 ddr_mem_dq_4 t12 ddr_mem_dq_5 r12 ddr_mem_dq_6 p12 ddr_mem_dq_7 p13 ddr_mem_dqs_0 lower data strobe o differential sstl_2/ sstl_18 u10 nddr_mem_dqs_0 t10 ddr_mem_dm_0 lower data mask o sstl_2/ sstl_18 u12 ddr_mem_gate_open_0 lower gate open io r10 ddr_mem_dq_8 data lines (upper byte) io t17 ddr_mem_dq_9 t16 ddr_mem_dq_10 u17 ddr_mem_dq_11 u16 ddr_mem_dq_12 u14 ddr_mem_dq_13 u13 ddr_mem_dq_14 t13 ddr_mem_dq_15 r13 ddr_mem_dqs_1 upper data strobe io differential sstl_2/ sstl_18 u15 nddr_mem_dqs_1 t15 ddr_mem_dm_1 upper data mask io sstl_2/ sstl_18 t14 ddr_mem_gate_open_1 upper gate open r14 ddr_mem_vref reference voltage i analog p10 ddr_mem_comp2v5_gndbgcomp return for external resistors power power r4 ddr_mem_comp2v5_rext external resistor power analog p4 ddr2_en configuration i ttl input buffer 3.3 v to l e r a n t , p u j13 table 12. ddr pins description (continued) signal name description dir. pin type ball spear320s pin description doc id 022508 rev 2 37/113 3.4 shared io pins (pl_gpios) the 98 pl_gpio and 4 pl_clk pins have the following characteristics: output buffer: ttl 3.3 v capable up to 10 ma input buffer: ttl, 3.3 v tolerant, selectable internal pull up/pull down (pu/pd) the pl_gpios can be c onfigured in different modes. this allows spear 320s to be tailored for use in various applications like: metering concentrators large power supply controllers small printers 3.4.1 pl_gpio / pl _clk pins description note: the i/o direction depend s on the currently configured multiplexing option and can be different from the i/o direction at re s et. refer to ta b l e 15: pl_gpio/pl_clk multiplexing s cheme and re s et s tate s . 3.4.2 extended mode: rmii automation networking mode when extended mode is selected the i/o functions can be selected individually from the columns of ta bl e 15 using 11 ras_iosel_regx registers which provide 3-bit configuration fields for selecting the i/o functions on each of the 102 gpio i/o pins. (see ta bl e 15: pl_gpio/pl_clk multiplexing s cheme and re s et s tate s ). this mode provides a fully flexible way of configuring the i/o functions for different applications. it is forward compatible with the 4 legacy configuration modes and features enhanced interrupt management with programmable edge polarity. for example: 3 independent ssp synchronous serial ports (spi, microwire or ti protocol) 2 rmii interfaces standard parallel port (spp device implementation) 3 independent i2c interfaces 7 uarts ? 1 with hardware flow control (up to 3 mbps) ? 1 with hardware flow control (baud rate up to 7 mbps) ? 5 with software flow control (baud rate up to 7 mbps) 4 pwm outputs table 13. pl_gpio / pl_clk pins description group signal name ball dir. description pin type pl_gpios pl_gpio_97... pl_gpio_0 (see table 15 ) io general purpose io or multiplexed pins (see table 15 ) (see the introduction of section 3.4 here above) pl_clk1... pl_clk4 programmable logic external clocks pin description spear320s 38/113 doc id 022508 rev 2 3.4.3 alternate functions other peripheral functions are listed in the alternate functions column of ta bl e 13: pl_gpio / pl_clk pin s de s cription and can be individually enabled/disabled configuring the bits of a dedicated control register. 3.4.4 legacy configuration modes this section describes the legacy operating modes created by using a selection of the embedded ips. these 4 modes provide for backward-compatib lity with existing spear320 hardware applications. mode 1 is the default mode for spear320s. the following modes can be selected by software through programming of dedicated configuration registers (see figure 3: hierarchical multiplexing s cheme ). mode 1: hmi automation mode mode 2: mii automation networking mode mode 3: expanded automation mode mode 4: printer mode ta bl e 15 shows the io functions available in each mode. mode 1 is the default mode for spear320s. mode 1: hmi automation mode in this example, hmi automation networking operating mode provides the following features with mode 1 selected and alternate functions for uart0, ssp0 and i2c0 enabled. other feature combinations are possible using different alternate functions. lcd interface (up to 1024x768, 24-bit lcd controller, tft and stn panels) nand flash interface (8 bits, 4 chip selects) 2 can 2.0 interfaces 3 uarts ? 1 with hardware flow control (up to 3 mbps) ? 2 with software flow control (baud rate up to 7 mbps) touchscreen facilities 3 independent ssp synchronous serial ports (spi, microwire or ti protocol) 2 independent i2c interfaces gpios with interrupt capability sdio interface supporting spi, sd1, sd4 and sd8 mode 1 pwm output (pwm3) spear320s pin description doc id 022508 rev 2 39/113 mode 2: mii automation networking mode in this example, mii automation networking operating mode provides the following features with mode 2 selected and alternate functions for uart0, mii0, ssp0, i2c0 enabled. other feature combinations are possible using different alternate functions. nand flash interface (8 bits, 4 chip selects) 2 can 2.0 interfaces 2 mii interfaces 7 uarts ? 1 with hardware flow control (up to 3 mbps) ? 6 with software flow control (baud rate up to 7 mbps) 3 independent ssp synchronous serial ports (spi, microwire or ti protocol) with 3 independent cs. 2 independent i2c interfaces gpios with interrupt capability sdio interface supporting spi, sd1, sd4 and sd8 mode mode 3: expanded automation mode in this example, expanded automation operating mode provides the following features with mode 3 selected and alternat e functions for mii0, uart0, i2c0 and ssp0 enabled. some features are mutually exclusive. note that if uart0 alternate functions with software flow control are enabled, uart3/4/5 are available, but not if uart0 alternate functions are enabled with hardware flow control. if ssp0 alternate functions ar e enabled, pwm0/1/2/3 are not available. this is also the case fo r emi with respect to the nand flash interface (fsmc). other feature combinations are possible using different alternate functions. external memory interface (16 data bits, 24 address bits and 4 chip selects) fsmc nand flash interface (8-16 bits and 4 chip selects shared with emi) 2 can 2.0 interfaces mii interface 6 uarts ? 1 with hardware flow control (up to 3 mbps) ? 1 with hardware flow control (baud rate up to 7 mbps) ? 4 with software flow control (baud rate up to 7 mbps) 1 ssp port 2 independent i2c interfaces up to 4 pwm outputs gpios with interr upt capabilities pin description spear320s 40/113 doc id 022508 rev 2 mode 4: printer mode in this example, printer mode provides the following features with mode 4 selected and alternate functions for uart0, i2c0 and ssp0 enabled. other feature combinations are possible using different alternate functions. nand flash interface (8 bits, 4 chip selects) 4 pwm outputs 7 uarts ? 1 with hardware flow control (up to 3 mbps) ? 1 with hardware flow control (baud rate up to 7 mbps) ? 5 with software flow control (baud rate up to 7 mbps) sdio interface supporting spi, sd1, sd4 and sd8 mode standard parallel port (spp device implementation) 2 independent ssp synchronous serial ports (spi, microwire or ti protocol) 2 independent i2c interfaces gpios with interr upt capabilities spear320s pin description doc id 022508 rev 2 41/113 3.4.5 boot pins the status of the boot pins is read at startup by the bootrom. the h[7:0] pins are user-definable strapping option pins. the values of the pins are latched at startup and are readable from a register. 3.4.6 gpios the pl_gpio pins can be used as software-controlled general purpose i/os if they are not used by the interfaces of embedded ips mapped on same pins. table 14. boot pins description b3 b2 b1 b0 boot device 0000 usb device 0001 ethernet mii0 (mac address in i2c non-volatile memory) 0010 ethernet mii0 (mac address in spi non-volatile memory) 0011 serial nor flash (smi interface) 0100 parallel 8-bit nor flash (emi interface) 0101 parallel 16-bit nor flash (emi interface) 0110 parallel 8-bit nand flash (fsmc interface) 0111 parallel 16-bit nand flash (fsmc interface) 1010 uart0 1011 bypass bootrom and boot from serial nor flash (smi interface) other reserved pin description spear320s 42/113 doc id 022508 rev 2 3.4.7 multiplexing scheme to provide the best i/o multiplexing flexib ility and the higher number of gpios for arm controlled input-output function, the following hierarchical multiplexing scheme has been implemented. figure 3. hierarchical multiplexing scheme note: 3 s election bit s per pin are available in ras_io s el_reg (0..10). alternate functions ras_select_reg gpio_select (0..3) registers gpios extended mode mode 1: hmi automation mode 2: mii automation neworking mode 3: expanded automation mode 4: printer legacy modes extended mode enable extcontrol_reg[0] legacy mode select control_reg (0.. 2) extended mode selector ras_iosel_ reg (0 ..10) 3 3 15 pin description spear320s 43/113 doc id 022508 rev 2 table 15. pl_gpio/pl_clk multiplexing scheme and reset states pl_gpio_# / ball number extended mode primary function (sw defined) alternate function (sw defined) full debug mode reset state boot pins function in gpio alternate mode legacy configuration mode (sw defined) mode 1 (default configuration after reset) mode 2 mode 3 mode 4 pl_gpio_97/h16 ssp1_mosi arm_trace_clk ol gpio_97 cld0 mii1_txclk emi_a0 i2c2_sda pl_gpio_96/h15 ssp1_clk arm_trace_pkta[0] ol gpio_96 cld1 mii1_txd0 emi_a1 i2c2_scl pl_gpio_95/h14 ssp1_ss0 arm_trace_pkta[1] ol gpio_95 cld2 mii1_txd1 emi_a2 uart3_tx pl_gpio_94/h13 ssp1_miso arm_trace_pkta[2] ol gpio_94 cld3 mii1_txd2 emi_a3 uart3_rx pl_gpio_93/g17 ssp2_mosi arm_trace_pkta[3] ol gpio_93 cld4 mii1_txd3 emi_a4 uart4_tx pl_gpio_92/g16 ssp2_clk arm_trace_pktb[0] ol gpio_92 cld5 mii1_txen emi_a5 uart4_rx pl_gpio_91/g15 ssp2_ss0 arm_trace_pktb[1] ol gpio_91 cld6 mii1_txer emi_a6 uart5_tx pl_gpio_90/g14 ssp2_miso arm_trace_pktb[2] ol gpio_90 cld7 mii1_rxclk emi_a7 uart5_rx pl_gpio_89/f17 pwm0 arm_trace_pktb[3] ol gpio_89 cld8 mii1_rxdv emi_a8 uart6_tx pl_gpio_88/f16 pwm1 arm_trace_synca ol gpio_88 cld9 mii1_rxer emi_a9 uart6_rx pl_gpio_87/g13 pwm2 arm_trace_syncb ol gpio_87 cld10 mii1_rxd0 emi_a10 0 pl_gpio_86/e17 pwm3 arm_pipestata[0] ol gpio_86 cld11 mii1_rxd1 emi_a11 0 pl_gpio_85/f15 uart1_cts arm_pipestata[1] ol gpio_85 cld12 mii1_rxd2 emi_a12 spp_data0 pl_gpio_84/d17 uart1_dtr arm_pipestata[2] ol gpio_84 cld13 mii1_rxd3 emi_a13 spp_data1 pl_gpio_83/e16 uart1_ri arm_pipestatb[0] ol gpio_83 cld14 mii1_col emi_a14 spp_data2 pl_gpio_82/e15 uart1_dcd arm_pipestatb[1] ol gpio_82 cld15 mii1_crs emi_a15 spp_data3 pl_gpio_81/c17 uart1_dsr arm_pipestatb[2] ol gpio_81 cld16 mii1_mdio emi_a16 spp_data4 pl_gpio_80/d16 uart1_rts arm_trace_pkta[4] ol gpio_80 cld17 mii1_mdc emi_a17 spp_data5 pl_gpio_79/f14 uart_rs485_tx arm_trace_pkta[5] ol gpio_79 cld18 0 emi_a18 spp_data6 pl_gpio_78/d15 uart_rs485_rx arm_trace_pkta[6] ol gpio_78 cld19 0 emi_a19 spp_data7 pl_gpio_77/b17 uart_rs485_oe arm_trace_pkta[7] ol gpio_77 cld20 0 emi_a20 spp_strbn pl_gpio_76/f13 i2c2_sda arm_trace_pktb[4] ol gpio_76 cld21 0 emi_a21 spp_ackn pl_gpio_75/e14 i2c2_scl arm_trace_pktb[5] ol gpio_75 cld22 0 emi_a22 spp_busy spear320s pin description doc id 022508 rev 2 44/113 pl_gpio_74/c16 uart3_tx arm_trace_pktb[6] ol gpio_74 cld23 0 emi_a23 spp_perror pl_gpio_73/a17 uart3_rx arm_trace_pktb[7] ol gpio_73 clac 0 emi_d8/ fsmc_d8 spp_select pl_gpio_72/b16 uart4_tx functional mode ol gpio_72 clfp 0 emi_d9/ fsmc_d9 spp_autofdn pl_gpio_71/d14 uart4_rx ol gpio_71 cllp 0 emi_d10/ fsmc_d10 spp_faultn pl_gpio_70/c15 uart5_tx ol gpio_70 clle 0 emi_d11/ fsmc_d11 spp_initn pl_gpio_69/a16 uart5_rx ol gpio_69 clpower 0 emi_wait spp_selinn pl_gpio_68/b15 ssp1_mosi ipu gpio_68 fsmc_d0 fsmc_d0 emi_d0/ fsmc_d0 fsmc_d0 pl_gpio_67/c14 ssp1_clk ipu gpio_67 fsmc_d1 fsmc_d1 emi_d1/ fsmc_d1 fsmc_d1 pl_gpio_66/e13 ssp1_ss0 ipu gpio_66 fsmc_d2 fsmc_d2 emi_d2/ fsmc_d2 fsmc_d2 pl_gpio_65/b14 ssp1_miso ipu gpio_65 fsmc_d3 fsmc_d3 emi_d3/ fsmc_d3 fsmc_d3 pl_gpio_64/d13 ssp2_mosi ipu gpio_64 fsmc_d4 fsmc_d4 emi_d4/ fsmc_d4 fsmc_d4 pl_gpio_63/c13 ssp2_clk ipu gpio_63 fsmc_d5 fsmc_d5 emi_d5/ fsmc_d5 fsmc_d5 pl_gpio_62/a15 ssp2_ss0 ipu h7 gpio_62 fsmc_d6 fsmc_d6 emi_d6/ fsmc_d6 fsmc_d6 pl_gpio_61/e12 ssp2_miso ipu h6 gpio_61 fsmc_d7 fsmc_d7 emi_d7/ fsmc_d7 fsmc_d7 pl_gpio_60/a14 pwm0 ipu h5 gpio_60 fsmc_addr_le fsmc_addr_le fsmc_addr_le fsmc_addr_le pl_gpio_59/b13 pwm1 ipu h4 gpio_59 fsmc_we fsmc_we emi_we/ fsmc_we fsmc_we pl_gpio_58/d12 pwm2 ipu h3 gpio_58 fsmc_re fsmc_re emi_oe/ fsmc_re fsmc_re pl_gpio_57/e11 pwm3 ipu h2 gpio_57 fsmc_cmd_ le fsmc_cmd_ le fsmc_cmd_le fsmc_cmd_le pl_gpio_56/c12 ipu h1 gpio_56 fsmc_rdy /bsy fsmc_rdy/ bsy fsmc_rdy/bsy fsmc_rdy/ bsy pl_gpio_55/a13 ipu h0 gpio_55 fsmc_cs0 fsmc_cs0 emi_ce0/ fsmc_cs0 fsmc_cs0 pl_gpio_54/e10 ipu b3 gpio_54 fsmc_cs1 fsmc_cs1 emi_ce1/ fsmc_cs1 fsmc_cs1 pl_gpio_53/d11 uart3_tx ipu b2 gpio_53 fsmc_cs2 fsmc_cs2 emi_ce2/ fsmc_cs2 fsmc_cs2 table 15. pl_gpio/pl_clk multiplexing scheme and reset states (continued) pl_gpio_# / ball number extended mode primary function (sw defined) alternate function (sw defined) full debug mode reset state boot pins function in gpio alternate mode legacy configuration mode (sw defined) mode 1 (default configuration after reset) mode 2 mode 3 mode 4 pin description spear320s 45/113 doc id 022508 rev 2 pl_gpio_52/b12 uart3_rx functional mode ipu b1 gpio_52 fsmc_cs3 fsmc_cs3 emi_ce_3/ fsmc_cs3 fsmc_cs3 pl_gpio_51/d10 ssp1_mosi ipu b0 gpio_51 sd_cd sd_cd emi_byten0 sd_cd pl_gpio_50/a12 ssp1_clk tmr_cptr4 ipu gpio_50 sd_dat7 sd_dat7 emi_byten1 sd_dat7 pl_gpio_49/c11 ssp1_ss0 tmr_cptr3 ipu gpio_49 sd_dat6 sd_dat6 emi_d12/ fsmc_d12 sd_dat6 pl_gpio_48/b11 ssp1_miso tmr_cptr2 ipu gpio_48 sd_dat5 sd_dat5 emi_d13/ fsmc_d13 sd_dat5 pl_gpio_47/c10 ssp2_mosi tmr_cptr1 ipu gpio_47 sd_dat4 sd_dat4 emi_d14/ fsmc_d14 sd_dat4 pl_gpio_46/a11 ssp2_clk tmr_clk4 ol gpio_46 sd_dat3 sd_dat3 emi_d15/ fsmc_d15 sd_dat3 pl_gpio_45/b10 ssp2_ss0 tmr_clk3 ol gpio_45 sd_dat2 sd_dat2 uart1_dcd sd_dat2 pl_gpio_44/a10 ssp2_miso tmr_clk2 ol gpio_44 sd_dat1 sd_dat1 uart1_dsr sd_dat1 pl_gpio_43/e9 pwm0 tmr_clk1 ol gpio_43 sd_dat0 sd_dat0 uart1_rts sd_dat0 pl_gpio_42/d9 pwm1 uart0_dtr oh gpio_42 i2s_rx i2s_rx uart3_tx 0 pl_gpio_41/c9 pwm2 uart0_ri ipd gpio_41 i2s_tx i2s_tx uart3_rx 0 pl_gpio_40/b9 pwm3 uart0_dsr ipd gpio_40 i2s_lr i2s_lr uart4_tx 0 pl_gpio_39/a9 ssp1_mosi uart0_dcd ipd gpio_39 i2s_clk i2s_clk uart4_rx 0 pl_gpio_38/a8 ssp1_clk uart0_cts ipd gpio_38 pwm0 pwm0 uart5_tx 0 pl_gpio_37/b8 ssp1_ss0 uart0_rts oh gpio_37 pwm1 pwm1 uart5_rx 0 pl_gpio_36/c8 ssp1_miso ssp0_cs4 oh gpio_36 touchscreen x 0 uart1_cts uart1_cts pl_gpio_35/d8 ssp2_mosi ssp0_cs3 oh gpio_35 audio_over_samp_ clk audio_over_samp_ clk uart1_dtr uart1_dtr pl_gpio_34/e8 ssp2_clk ssp0_cs2 oh gpio_34 sd_led / pwm2 sd_led / pwm2 uart1_ri uart1_ri pl_gpio_33/e7 ssp2_ss0 basgpio5 ipu gpio_33 can0_tx can0_tx can0_tx uart1_dcd pl_gpio_32/d7 ssp2_miso basgpio4 ipu gpio_32 can0_rx can0_rx can0_rx uart1_dsr pl_gpio_31/c7 pwm0 basgpio3 ipu gpio_31 can1_tx can1_tx can1_tx uart1_rts pl_gpio_30/b7 pwm1 basgpio2 ipu gpio_30 can1_rx can1_rx can1_rx 0 table 15. pl_gpio/pl_clk multiplexing scheme and reset states (continued) pl_gpio_# / ball number extended mode primary function (sw defined) alternate function (sw defined) full debug mode reset state boot pins function in gpio alternate mode legacy configuration mode (sw defined) mode 1 (default configuration after reset) mode 2 mode 3 mode 4 spear320s pin description doc id 022508 rev 2 46/113 pl_gpio_29/a7 pwm2 basgpio1 functional mode ipu gpio_29 uart1_tx uart1_tx uart1_tx uart1_tx pl_gpio_28/a6 pwm3 basgpio0 ipu gpio_28 uart1_rx uart1_rx uart1_rx uart1_rx pl_gpio_27/b6 rmii0_txd0 mii0_txclk ipu gpio_27 reserved 0 reserved reserved pl_gpio_26/a5 rmii0_rxd0 mii0_txd0 ol gpio_26 reserved 0 reserved reserved pl_gpio_25/c6 rmii1_txd0 mii0_txd1 ol gpio_25 reserved 00reserved pl_gpio_24/b5 rmii1_rxd0 mii0_txd2 ol gpio_24 reserved 00reserved pl_gpio_23/a4 rmii1_tx_en mii0_txd3 ol gpio_23 reserved 0 reserved reserved pl_gpio_22/d6 rmii_ref_clk mii0_txen ol gpio_22 reserved 0 reserved reserved pl_gpio_21/c5 rmii1_txd1 mii0_txer ol gpio_21 reserved 0 reserved reserved pl_gpio_20/b4 rmii1_rxd1 mii0_rxclk ipu gpio_20 ssp1_mosi i2c2_sda 0 ssp1_mosi pl_gpio_19/a3 rmii1_crs_dv mii0_rxdv ipu gpio_19 ssp1_clk i2c2_scl 0 ssp1_clk pl_gpio_18/d5 rmii1_rx_er mii0_rxer ipu gpio_18 ssp1_ss0 0 0 ssp1_ss0 pl_gpio_17/c4 rmii0_txd1 mii0_rxd0 ipu gpio_17 ssp1_miso 0 0 ssp1_miso pl_gpio_16/e6 rmii0_tx_en mii0_rxd1 ipu gpio_16 ssp2_mosi uart3_tx 0 0 pl_gpio_15/b3 rmii0_rxd1 mii0_rxd2 ipu gpio_15 ssp2_clk uart3_rx pwm0 pwm0 pl_gpio_14/a2 rmii0_crs_dv mii0_rxd3 ipu gpio_14 ssp2_ss0 uart4_tx pwm1 pwm1 pl_gpio_13/a1 rmii0_rx_er mii0_col ipu gpio_13 ssp2_miso uart4_rx pwm2 pwm2 pl_gpio_12/d4 sd_cd mii0_crs ipu gpio_12 pwm3 0 pwm3 pwm3 pl_gpio_11/e5 rmii_mdc mii0_mdc ol gpio_11 reserved 0 reserved reserved pl_gpio_10/c3 rmii_mdio mii0_mdio ipd gpio_10 reserved 0 reserved reserved pl_gpio_9/b2 i2c1_sda ssp0_mosi ipu gpio_9 0 uart3_tx pwm0 0 pl_gpio_8/c2 i2c1_scl ssp0_clk ol gpio_8 0 uart3_rx pwm1 0 pl_gpio_7/d3 uart1_cts ssp0_ss0 oh gpio_7 0 uart4_tx pwm2 0 pl_gpio_6/b1 uart1_dtr ssp0_miso ipu gpio_6 0 uart4_rx pwm3 0 table 15. pl_gpio/pl_clk multiplexing scheme and reset states (continued) pl_gpio_# / ball number extended mode primary function (sw defined) alternate function (sw defined) full debug mode reset state boot pins function in gpio alternate mode legacy configuration mode (sw defined) mode 1 (default configuration after reset) mode 2 mode 3 mode 4 pin description spear320s 47/113 doc id 022508 rev 2 note: 1 ta b l e 1 5 cell s filled with 0 or 1 are unu s ed and unle ss otherwi s e configured a s alternate function or gpio, the corre s ponding pin i s held at low or high level re s pectively by the internal logic. 2pin s s hared by emi and fsmc: depending on the ahb addre ss to be acce ss ed the pin s are u s ed for emi or fsmc tran s fer s . 3re s et s tate definition: the s tate of each pin during re s et and after re s et relea s e. device i s in configuration mode 1 (default s tate) : oh= output high level, ol output low leve l, ipu = input pull up, ipd = input pull down. 4 full debug mode: refer to table 32: ball s haring during debug for detail s on debug mode s election. 5 functional mode definition: in functional mode the i/o work s a s configured by the application (depending on s etting s for configuration mode 1- 4/extended mode/alternate function). 6 refer to ta bl e 1 6 : ta b l e s hading reference for table 15 multiplexing s cheme for color s and s hading u s ed in table 15 cell s to identify pin group s pl_gpio_5/d2 uart1_ri i2c0_sda functional mode ipu gpio_5 0 uart5_tx 0 0 pl_gpio_4/c1 uart1_dcd i2c0_scl ipu gpio_4 0 uart5_rx 0 0 pl_gpio_3/d1 uart1_dsr uart0_rx ipd gpio_3 i2c2_sda uart6_tx 0 0 pl_gpio_2/e4 uart1_rts uart0_tx oh gpio_2 i2c2_scl uart6_rx 0 0 pl_gpio_1/e3 i2c2_sda irda_rx ipu gpio_1 uart2_tx uart2_tx uart2_tx uart2_tx pl_gpio_0/f3 i2c2_scl irda_tx ol gpio_0 uart2_rx uart2_rx uart2_rx uart2_rx pl_clk1/k17 uart3_tx pl_clk1 ol gpio_98 clcp 0 i2c1_sda sd_led pl_clk2/j17 uart3_rx pl_clk2 ol gpio_99 sd_clk sd_clk i2c1_scl sd_clk pl_clk3/j16 uart4_tx pl_clk3 ipu gpio_100 sd_wp sd_wp 0 sd_wp pl_clk4/h17 uart4_rx pl_clk4 ipu gpio_101 sd_cmd sd_cmd 0 sd_cmd table 15. pl_gpio/pl_clk multiplexing scheme and reset states (continued) pl_gpio_# / ball number extended mode primary function (sw defined) alternate function (sw defined) full debug mode reset state boot pins function in gpio alternate mode legacy configuration mode (sw defined) mode 1 (default configuration after reset) mode 2 mode 3 mode 4 spear320s pin description doc id 022508 rev 2 48/113 table 16. table shading reference for table 15 multiplexing scheme shading pin group fsmc fsmc pins: nand flash emi emi pins clcd color lcd controller pins touchscreen touchscreen pins uart uart pins can can pins ethernet mac mii/rmii ethernet mac pins sd/sdio/mmc sd card controller pins pwm generators pulse-width modulator timer module pins gpt timer pins irda irda pins ssp ssp pins i2c i2c pins spp standard parallel port pins i2s i2s pins spear320s pin description doc id 022508 rev 2 49/113 3.4.8 multiplexed signals description this section provides a description of the multiplexed si gnals present in spear320s device, grouped by ip. table 17. fsmc signals description signal name description dir. pl_gpio_# /ball configuration mode fsmc_addr_le address latch enable (active high) o pl_gpio_60/a14 1, 2, 3, 4, extended fsmc_cmd_ le command latch enable (active high) o pl_gpio_57/e11 1, 2, 3, 4, extended fsmc_cs0 chip enable (active low) o pl_gpio_55/a13 1, 2, 3, 4, extended fsmc_cs1 pl_gpio_54/e10 1, 2, 3, 4, extended fsmc_cs2 pl_gpio_53/d11 1, 2, 3, 4, extended fsmc_cs3 pl_gpio_52/b12 1, 2, 3, 4, extended fsmc_d0 data lines io pl_gpio_68/b15 1, 2, 3, 4, extended fsmc_d1 pl_gpio_67/c14 1, 2, 3, 4, extended fsmc_d2 pl_gpio_66/e13 1, 2, 3, 4, extended fsmc_d3 pl_gpio_65/b14 1, 2, 3, 4, extended fsmc_d4 pl_gpio_64/d13 1, 2, 3, 4, extended fsmc_d5 pl_gpio_63/c13 1, 2, 3, 4, extended fsmc_d6 pl_gpio_62/a15 1, 2, 3, 4, extended fsmc_d7 pl_gpio_61/e12 1, 2, 3, 4, extended fsmc_d8 pl_gpio_73/a17 3, extended fsmc_d9 pl_gpio_72/b16 3, extended fsmc_d10 pl_gpio_71/d14 3, extended fsmc_d11 pl_gpio_70/c15 3, extended fsmc_d12 pl_gpio_49/c11 3, extended fsmc_d13 pl_gpio_48/b11 3, extended fsmc_d14 pl_gpio_47/c10 3, extended fsmc_d15 pl_gpio_46/a11 4, extended fsmc_rdy/bsy wait signal (active low) i pl_gpio_56/c12 1, 2, 3, 4, extended fsmc_re read enable (active low) o pl_ gpio_58/d12 1, 2, 3, 4, extended fsmc_we write enable (active low) o p l_gpio_59/b13 1, 2, 3, 4, extended pin description spear320s 50/113 doc id 022508 rev 2 table 18. emi signals description signal name description dir. pl_gp io_# /ball configuration mode emi_a0 address bus o pl_gpio_97/h16 3, extended emi_a1 pl_gpio_96/h15 3, extended emi_a2 pl_gpio_95/h14 3, extended emi_a3 pl_gpio_94/h13 3, extended emi_a4 pl_gpio_93/g17 3, extended emi_a5 pl_gpio_92/g16 3, extended emi_a6 pl_gpio_91/g15 3, extended emi_a7 pl_gpio_90/g14 3, extended emi_a8 pl_gpio_89/f17 3, extended emi_a9 pl_gpio_88/f16 3, extended emi_a10 pl_gpio_87/g13 3, extended emi_a11 pl_gpio_86/e17 3, extended emi_a12 pl_gpio_85/f15 3, extended emi_a13 pl_gpio_84/d17 3, extended emi_a14 pl_gpio_83/e16 3, extended emi_a15 pl_gpio_82/e15 3, extended emi_a16 pl_gpio_81/c17 3, extended emi_a17 pl_gpio_80/d16 3, extended emi_a18 pl_gpio_79/f14 3, extended emi_a19 pl_gpio_78/d15 3, extended emi_a20 pl_gpio_77/b17 3, extended emi_a21 pl_gpio_76/f13 3, extended emi_a22 pl_gpio_75/e14 3, extended emi_a23 pl_gpio_74/c16 3, extended emi_byten0 byte_enables ar e provided to validate the data present on the bus when high data is valid. io pl_gpio_51/d10 3, extended emi_byten1 pl_gpio_50/a12 3, extended emi_ce0 emi chip selects, derived from internal address decoding (kept disabled during nand_flash cycles) o pl_gpio_55/a13 3, extended emi_ce1 pl_gpio_54/e10 3, extended emi_ce2 pl_gpio_53/d11 3, extended emi_ce3 pl_gpio_52/b12 3, extended spear320s pin description doc id 022508 rev 2 51/113 emi_d0 data bus o pl_gpio_68/b15 3, extended emi_d1 pl_gpio_67/c14 3, extended emi_d2 pl_gpio_66/e13 3, extended emi_d3 pl_gpio_65/b14 3, extended emi_d4 pl_gpio_64/d13 3, extended emi_d5 pl_gpio_63/c13 3, extended emi_d6 pl_gpio_62/a15 3, extended emi_d7 pl_gpio_61/e12 3, extended emi_d8 pl_gpio_73/a17 3, extended emi_d9 pl_gpio_72/b16 3, extended emi_d10 pl_gpio_71/d14 3, extended emi_d11 pl_gpio_70/c15 3, extended emi_d12 pl_gpio_49/c11 3, extended emi_d13 pl_gpio_48/b11 3, extended emi_d14 pl_gpio_47/c10 3, extended emi_d15 pl_gpio_46/a11 3, extended emi_oe data output enable for read cycles, target device must open its data bus with this signal. o pl_gpio_58/d12 3, extended emi_wait transfer acknowledge signal, used by the cycle target to slow down the cycle (must be pulled up on the bus for targets that do not need it). note: thi s i s an optional s ignal. i pl_gpio_69/a16 3, extended emi_we write strobe, data are ready on emi_adb before its falling edge and after the rising edge. o pl_gpio_59/b13 3, extended table 18. emi signals description (continued) signal name description dir. pl_gp io_# /ball configuration mode pin description spear320s 52/113 doc id 022508 rev 2 table 19. clcd signals description signal name description dir. pl_gpio_# /ball c onfiguration mode clac stn ac bias drive or tft data enable output o pl_gpio_73/a17 1, extended clcp lcd panel clock o pl_clk1/k17 1, extended cld0 lcd panel data o pl_gpio_97/h16 1, extended cld1 pl_gpio_96/h15 cld2 pl_gpio_95/h14 cld3 pl_gpio_94/h13 cld4 pl_gpio_93/g17 cld5 pl_gpio_92/g16 cld6 pl_gpio_91/g15 cld7 pl_gpio_90/g14 cld8 pl_gpio_89/f17 cld9 pl_gpio_88/f16 cld10 pl_gpio_87/g13 cld11 pl_gpio_86/e17 cld12 pl_gpio_85/f15 cld13 pl_gpio_84/d17 cld14 pl_gpio_83/e16 cld15 pl_gpio_82/e15 cld16 pl_gpio_81/c17 cld17 pl_gpio_80/d16 cld18 pl_gpio_79/f14 cld19 pl_gpio_78/d15 cld20 pl_gpio_77/b17 cld21 pl_gpio_76/f13 cld22 pl_gpio_75/e14 cld23 pl_gpio_74/c16 clfp frame pulse (stn)/ vertical synchronization pulse (tft) o pl_gpio_72/b16 1, extended clle line end signal o pl_gpio_70/c15 1, extended cllp line synchronization pulse (stn)/ horizontal synchronization pulse (tft) o pl_gpio_71/d14 1, extended clpower lcd panel power enable o pl_gpio_69/a16 1, extended spear320s pin description doc id 022508 rev 2 53/113 table 20. touchscreen signal description signal name description dir. pl_gpio_# /ball configuration mode touchscreen x touchscreen select signal o pl_gpio_36/c8 1, extended table 21. uart signals description signal name description dir. pl_gpio_# /ball configuration mode uart0 uart0_cts uart0 clear to send modem status input i pl_gpio_38/a8 alternate function uart0_dcd uart0 data carrier detect modem status input i pl_gpio_39/a9 alternate function uart0_dsr uart0 data set ready modem status input i pl_gpio_40/b9 alternate function uart0_dtr uart0 data terminal ready modem status output o pl_gpio_42/d9 alternate function uart0_ri uart0 ring indicator modem status input i pl_gpio_41/c9 alternate function uart0_rts uart0 request to send modem status output o pl_gpio_37/b8 alternate function uart0_rx uart0 received serial data input i pl_gpio_3/d1 alternate function uart0_tx uart0 transmitted serial data output o pl_gpio_2/e4 alternate function uart1 uart1_cts uart1 clear to send modem status input i pl_gpio_36/c8 3, 4, extended pl_gpio_85/f15 extended mode pl_gpio_7/d3 uart1_dcd uart1 data carrier detect modem status input i pl_gpio_45/b10 3, extended pl_gpio_33/e7 4, extended pl_gpio_4/c1 extended mode pl_gpio_82/e15 uart1_dsr uart1 data set ready modem status input i pl_gpio_44/a10 3, extended pl_gpio_32/d7 4, extended pl_gpio_3/d1 extended mode pl_gpio_81/c17 uart1_dtr uart1 data terminal ready modem status output o pl_gpio_35/d8 3, 4, extended pl_gpio_84/d17 extended mode pl_gpio_6/b1 uart1_ri uart1 ring indicator modem status input i pl_gpio_34/e8 3, 4 , extended pl_gpio_83/e16 extended mode pl_gpio_5/d2 pin description spear320s 54/113 doc id 022508 rev 2 uart1_rts uart1 request to send modem status output o pl_gpio_43/e9 3, extended pl_gpio_31/c7 4, extended pl_gpio_80/d16 extended mode pl_gpio_2/e4 uart1_rx uart1 received serial data input i pl_gpio_28/a6 1, 2, 3, 4, extended uart1_tx uart1 transmitted serial data ou tput o pl_gpio_29/a7 1, 2, 3, 4, extended uart2 uart2_rx uart2 received serial data i nput i pl_gpio_0/f3 1, 2, 3, 4, extended uart2_tx uart2 transmitted serial data ou tput o pl_gpio_1/e3 1, 2, 3, 4, extended uart3 uart3_rx uart3 received serial data input i pl_gpio_15/b3 2, extended pl_gpio_8/c2 pl_gpio_41/c9 3, extended pl_gpio_94/h13 4, extended pl_gpio_73/a17 extended mode pl_gpio_52/b12 pl_clk2/j17 uart3_tx uart3 transmitted serial data output o pl_gpio_16/e6 2, extended pl_gpio_9/b2 pl_gpio_42/d9 3, extended pl_gpio_95/h14 4, extended pl_gpio_74/c16 extended mode pl_gpio_53/d11 pl_clk1/k17 uart4 uart4_rx uart4 received serial data input i pl_gpio_13/a1 2, extended pl_gpio_6/b1 pl_gpio_39/a9 3, extended pl_gpio_92/g16 4, extended i pl_gpio_71/d14 extended mode pl_clk4/h17 table 21. uart signals description (continued) signal name description dir. pl_gpio_# /ball configuration mode spear320s pin description doc id 022508 rev 2 55/113 uart4_tx uart4 transmitted serial data output o pl_gpio_14/a2 2, extended pl_gpio_7/d3 pl_gpio_40/b9 3, extended pl_gpio_93/g17 4, extended pl_gpio_72/b16 extended mode pl_clk3/j16 uart5 uart5_rx uart5 received serial data input i pl_gpio_4/c1 2, extended pl_gpio_37/b8 3, extended pl_gpio_90/g14 4, extended pl_gpio_69/a16 extended mode uart5_tx uart5 transmitted serial data output o pl_gpio_5/d2 2, extended pl_gpio_38/a8 3, extended pl_gpio_91/g15 4, extended pl_gpio_70/c15 extended mode uart6 uart6_rx uart6 received serial data input i pl_gpio_2/e4 2, extended pl_gpio_88/f16 4, extended uart6_tx uart6 transmitted serial data output o pl_gpio_3/d1 2, extended pl_gpio_89/f17 4, extended uart/rs485 uart_rs485_tx uart/rs485 transmitted serial data output o pl_gpio_79/f14 extended mode uart_rs485_rx uart/rs485 received serial data output i pl_gpio_78/d15 extended mode uart_rs485_oe uart/rs485 data output enable o pl_gpio_77/b17 extended mode table 21. uart signals description (continued) signal name description dir. pl_gpio_# /ball configuration mode table 22. can signals description signal name description dir. pl_gpio_# /ball configuration mode can0 can0_rx can0 receiver data input i p l_gpio_32/d7 1, 2, 3, extended can0_tx can0 transmitter data output o pl_gpio_33/e7 1, 2, 3, extended can1 can1_rx can1 receiver data input i p l_gpio_30/b7 1, 2, 3, extended can1_tx can1 transmitter data output o pl_gpio_31/c7 1, 2, 3, extended pin description spear320s 56/113 doc id 022508 rev 2 table 23. mmc-sd/sdio controller signals description signal name description dir. pl_gpio_# /ball configuration mode sd_cd card detection for single slot (active low) i pl_gpio_51/d10 1, 2, 4, extended pl_gpio_12/d4 extended mode sd_clk clock to external card o pl_clk2/j17 1, 2, 4, extended sd_cmd command line io pl_clk4/h17 1, 2, 4, extended sd_dat0 data line io pl_gpio_43/e9 1, 2, 4, extended sd_dat1 pl_gpio_44/a10 1, 2, 4, extended sd_dat2 pl_gpio_45/b10 1, 2, 4, extended sd_dat3 pl_gpio_46/a11 1, 2, 4, extended sd_dat4 pl_gpio_47/c10 1, 2, 4, extended sd_dat5 pl_gpio_48/b11 1, 2, 4, extended sd_dat6 pl_gpio_49/c11 1, 2, 4, extended sd_dat7 pl_gpio_50/a12 1, 2, 4, extended sd_led cautions the user not to remove the card while the sd card is being accessed. o pl_gpio_34/e8 1 , 2, extended pl_clk1/k17 4, extended sd_wp sd card write protect (active low) i pl_clk3/j16 1, 2, 4, extended table 24. pwm signals description signal name description dir. pl_gpio_# /ball configuration mode pwm0 pwm0 output channel o pl_gpio_38/a8 1 , 2, extended pl_gpio_15/b3 3 , 4, extended pl_gpio_9/b2 3, extended pl_gpio_89/f17 extended mode pl_gpio_60/a14 pl_gpio_43/e9 pl_gpio_31/c7 pwm1 pwm1 output channel o pl_gpio_37/b8 1 , 2, extended pl_gpio_14/a2 3 , 4, extended pl_gpio_8/c2 3, extended pl_gpio_88/f16 extended mode pl_gpio_59/b13 pl_gpio_42/d9 pl_gpio_30/b7 spear320s pin description doc id 022508 rev 2 57/113 pwm2 pwm2 output channel o pl_gpio_34/e8 1 , 2, extended pl_gpio_13/a1 3 , 4, extended pl_gpio_7/d3 3, extended pl_gpio_87/g13 extended mode pl_gpio_58/d12 pl_gpio_41/c9 pl_gpio_29/a7 pwm3 pwm3 output channel o pl_gpio_12/d4 1, 3, 4, extended pl_gpio_6/b1 3, extended pl_gpio_86/e17 extended mode pl_gpio_57/e11 pl_gpio_40/b9 pl_gpio_28/a6 table 24. pwm signals description (continued) signal name description dir. pl_gpio_# /ball configuration mode table 25. gpt signals description signal name description dir. pl_gpio_# /ball configuration mode tmr_clk1 this clock toggles each time the timer interrupt goes active. o pl_gpio_43/e9 alternate function tmr_clk2 pl_gpio_44/a10 alternate function tmr_clk3 pl_gpio_45/b10 alternate function tmr_clk4 pl_gpio_46/a11 alternate function tmr_cptr1 asynchronous signal provided for the measurement of timing signals i pl_gpio_47/c10 alternate function tmr_cptr2 pl_gpio_48/b11 alternate function tmr_cptr3 pl_gpio_49/c11 alternate function tmr_cptr4 pl_gpio_50/a12 alternate function table 26. irda signals description signal name description dir. pl_gpio_# /ball configuration mode irda_rx irda receiver data input i pl_gpio_1/e3 alternate function irda_tx irda transmitter data outp ut o pl_gpio_0/f3 alternate function pin description spear320s 58/113 doc id 022508 rev 2 table 27. ssp signals description signal name description dir. pl_gpio_# /ball configuration mode ssp0 ssp0_cs2 slave select (used only in master mode) o pl_gpio_34/e8 alternate function ssp0_cs3 slave select (used only in master mode) o pl_gpio_35/d8 alternate function ssp0_cs4 slave select (used only in master mode) o pl_gpio_36/c8 alternate function ssp0_clk ssp clock. it is us ed as output in master mode as input in slave mode. io pl_gpio_8/c2 alternate function ssp0_miso master input slave output io pl_gpio_6/b1 alternate function ssp0_mosi master output slave input io pl_gpio_9/b2 alternate function ssp0_ss0 ssp frame output (master mode), input (slave mode) io pl_gpio_7/d3 alternate function ssp1 ssp1_clk ssp clock. it is us ed as output in master mode as input in slave mode. io pl_gpio_19/a3 1 , 4, extended pl_gpio_96/h15 extended mode pl_gpio_67/c14 pl_gpio_50/a12 pl_gpio_38/a8 ssp1_miso master input slave output io pl_gpio_17/c4 1, 4, extended pl_gpio_94/h13 extended mode pl_gpio_65/b14 pl_gpio_48/b11 pl_gpio_36/c8 ssp1_mosi master output slave input io pl_gpio_20/b4 1 , 4, extended pl_gpio_97/h16 extended mode pl_gpio_68/b15 pl_gpio_51/d10 pl_gpio_39/a9 ssp1_ss0 ssp frame output (master mode), input (slave mode) io pl_gpio_18/d5 1, 4, extended pl_gpio_95/h14 extended mode pl_gpio_66/e13 pl_gpio_49/c11 pl_gpio_37/b8 ssp2 spear320s pin description doc id 022508 rev 2 59/113 ssp2_clk ssp clock. it is us ed as output in master mode as input in slave mode. io pl_gpio_15/b3 1, extended pl_gpio_92/g16 extended mode pl_gpio_63/c13 pl_gpio_46/a11 pl_gpio_34/e8 ssp2_miso master input slave output io pl_gpio_13/a1 1, extended pl_gpio_90/g14 extended mode pl_gpio_61/e12 pl_gpio_44/a10 pl_gpio_32/d7 ssp2_mosi master output slave input io pl_gpio_16/e6 1, extended pl_gpio_47/c10 extended mode pl_gpio_35/d8 pl_gpio_16/e6 pl_gpio_93/g17 pl_gpio_64/d13 ssp2_ss0 ssp frame output (master mode), input (slave mode) io pl_gpio_14/a2 1, extended pl_gpio_91/g15 extended mode pl_gpio_62/a15 pl_gpio_45/b10 pl_gpio_33/e7 table 27. ssp signals de scription (continued) signal name description dir. pl_gpio_# /ball configuration mode pin description spear320s 60/113 doc id 022508 rev 2 table 28. i2c signals description signal name description dir. pl_gpio_# /ball configuration mode i2c0 i2c0_scl i2c0 input/output clock i o pl_gpio_4/c1 alternate function i2c0_sda i2c0 input/output data i o pl_gpio_5/d2 alternate function i2c1 i2c1_scl i2c1 input/output clock io pl_clk2/j17 3, extended pl_gpio_8/c2 extended mode i2c1_sda i2c1 input/output data io pl_clk1/k17 3, extended pl_gpio_9/b2 extended mode i2c2 i2c2_scl i2c2 input/output clock io pl_gpio_2/e4 1, extended pl_gpio_19/a3 2, extended pl_gpio_96/h15 4, extended pl_gpio_75/e14 extended mode pl_gpio_0/f3 i2c2_sda i2c2 input/output data io pl_gpio_3/d1 1, extended pl_gpio_20/b4 2, extended pl_gpio_97/h16 4, extended pl_gpio_76/f13 extended mode pl_gpio_1/e3 table 29. i2s signals description signal name description dir. pl_gpio_# /ball configuration mode audio_over_samp_clk audio oversampling clock. this is the clock that i2s_clk derives from. the interfacing digital-to-analog converter (dac) can use this clock to (over)sample the i2s data. o pl_gpio_35/d8 1, 2, extended i2s_clk i2s clock o pl_gpi o_39/a9 1, 2, extended i2s_lr i2s word select o pl_gpio_40/b9 1, 2, extended i2s_rx i2s receive data i pl_gpio_42/d9 1, 2, extended i2s_tx i2s transmit data o pl_g pio_41/c9 1, 2, extended spear320s pin description doc id 022508 rev 2 61/113 table 30. spp signals description signal name description dir. pl_gpio_# /ball configuration mode spp_ackn the peripheral pulses this line low when it has received the previous data and is ready to receive more data. the rising edge of spp_ackn can be enabled to interrupt the host. o pl_gpio_76/f13 4, extended spp_autofdn usage of this line varies. most printers will perform a line feed after each carriage return when this line is low, and carriage returns only when this line is high. i pl_gpio_72/b16 4, extended spp_busy the peripheral drives this signal high to indicate that it is not ready to receive data. o pl_gpio_75/e14 4, extended spp_data0 spp unidirectional data lines o pl_gpio_85/f15 4, extended spp_data1 pl_gpio_84/d17 4, extended spp_data2 pl_gpio_83/e16 4, extended spp_data3 pl_gpio_82/e15 4, extended spp_data4 pl_gpio_81/c17 4, extended spp_data5 pl_gpio_80/d16 4, extended spp_data6 pl_gpio_79/f14 4, extended spp_data7 pl_gpio_78/d15 4, extended spp_faultn usage of this line varies. peripherals usually drive this line low when an error condition exists. o pl_gpio_71/d14 4, extended spp_initn this line is held low for a minimum of 50 s to reset the printer and clear the print buffer. i pl_gpio_70/c15 4, extended spp_perror usage of this line varies. printers typically drive this signal high during a paper empty condition. o pl_gpio_74/c16 4, extended spp_select the peripheral drives this signal high when it is selected and ready for data transfer. o pl_gpio_73/a17 4, extended spp_selinn the host drives this line low to select the peripheral. i pl_gpio_69/a16 4, extended spp_strbn data is valid during an active low pulse on this line. i pl_gpio_77/b17 4, extended pin description spear320s 62/113 doc id 022508 rev 2 table 31. ethernet signals description signal name description dir. pl_gpio_# / ball number configuration mode (see section 3.4.2 ) mii0 mii0_col phy collision this signal is assert ed by the phy when a collision is detected on the medium. this signal is not synchronous to any clock. (active high) i pl_gpio_13/a1 alternate function mii0_crs phy crs this signal is assert ed by the phy when either the transmit or receive medium is not idle. the phy deasserts this signal when both transmit and receive medium are idle. this signal is not synchronous to any clock. (active high) i pl_gpio_12/d4 alternate function mii0_mdc management data clock the mac provides timing reference for the mac_mdio signal through this aperiodic clock. the maximum frequency of this clock is 2.5 mhz.this clock is generated from the application clock (hclk) via a clock divider. o pl_gpio_11/e5 alternate function mii0_mdio management data input/output io pl_gpio_10/c3 alternate function mii0_rxclk reception clock this is the reception clock (25/2.5 mhz in 100m/10mbps) provided by the external phy for mii interfaces. the mii0_rxdn signals that the ethernet controller receives are synchronous to this clock. i pl_gpio_20/b4 alternate function mii0_rxd0 phy receive data these bits provide the mii receive data nibble. the validity of the data is qualified with mii0_rxdv and mii0_rxer. i pl_gpio_17/c4 alternate function mii0_rxd1 pl_gpio_16/e6 alternate function mii0_rxd2 pl_gpio_15/b3 alternate function mii0_rxd3 pl_gpio_14/a2 alternate function mii0_rxdv phy receive data valid when high, indicates that the data on the mii0_rxdn bus is valid. it remains asserted continuously from the first recovered byte/nibble of the frame through the final recovered byte/nibble. i pl_gpio_19/a3 alternate function mii0_rxer phy receive error when high, indicates an error or carrier extension in the received frame on the mii0_rxdn bus. i pl_gpio_18/d5 alternate function spear320s pin description doc id 022508 rev 2 63/113 mii0_txclk transmission clock this is the transmi ssion clock (25/2.5 mhz in 100 m/10 mbps) provided by the external phy for the mii interface. all the mii0_txdn signals generated by the mac are synchronous to this clock. i pl_gpio_27/b6 alternate function mii0_txd0 phy transmit data. these bits provide the mii transmit data nibble. the validity of the data is qualified with mii0_txen and mii0_txer. o pl_gpio_26/a5 alternate function mii0_txd1 pl_gpio_25/c6 alternate function mii0_txd2 pl_gpio_24/b5 alternate function mii0_txd3 pl_gpio_23/a4 alternate function mii0_txen phy transmit data enable when high, it indicates that valid data is being transmitted on the mii0_txdn bus. o pl_gpio_22/d6 alternate function mii0_txer phy transmit error when high, indicates a transmit error or carrier extension on the mii0_txdn bus. o pl_gpio_21/c5 alternate function mii1 mii1_col phy collision this signal is assert ed by the phy when a collision is detected on the medium. this signal is not synchronous to any clock. (active high) i pl_gpio_83/e16 2, extended mii1_crs phy crs this signal is assert ed by the phy when either the transmit or receive medium is not idle. the phy deasserts this signal when both transmit and receive medium are idle. this signal is not synchronous to any clock. (active high) i pl_gpio_82/e15 2, extended mii1_mdc management data clock the mac provides timing reference for the mii1_mdio signal through this aperiodic clock. the maximum frequency of this clock is 2.5 mhz.this clock is generated inside the ethernet controller from the application clock (hclk) via a clock divider. o pl_gpio_80/d16 2, extended mii1_mdio management data input/out put io pl_gpio_81/c17 2, extended mii1_rxclk this is the reception clock (25/2.5 mhz in 100m/10mbps) provided by the external phy for mii interfaces. all mii1_rxdn signals that the ethernet controller receives are synchronous to this clock. i pl_gpio_90/g14 2, extended table 31. ethernet signals description (continued) signal name description dir. pl_gpio_# / ball number configuration mode (see section 3.4.2 ) pin description spear320s 64/113 doc id 022508 rev 2 mii1_rxd0 phy receive data these bits provide the mii receive data nibble. the validity of the data is qualified with mii1_rxdv and mii1_rxer. i pl_gpio_87/g13 2, extended mii1_rxd1 pl_gpio_86/e17 2, extended mii1_rxd2 pl_gpio_85/f15 2, extended mii1_rxd3 pl_gpio_84/d17 2, extended mii1_rxdv phy receive data valid when high, indicates that the data on the mii1_rxdn bus is valid. it remains asserted continuously from the first recovered byte/nibble of the frame through the final recovered byte/nibble. i pl_gpio_89/f17 2, extended mii1_rxer phy receive error when high, indicates an error or carrier extension in the received frame on the mii1_rxdn bus. i pl_gpio_88/f16 2, extended mii1_txclk transmission clock this is the transmi ssion clock (25/2.5 mhz in 100m/10mbps) provided by the external phy for the mii. all the mii transmission signals generated by the mac are synchronous to this clock. i pl_gpio_97/h16 2, extended mii1_txd0 phy transmit data. these bits provide the mii transmit data nibble. the validity of the data is qualified with mii1_txen and mii1_txer. o pl_gpio_96/h15 2, extended mii1_txd1 pl_gpio_95/h14 2, extended mii1_txd2 pl_gpio_94/h13 2, extended mii1_txd3 pl_gpio_93/g17 2, extended mii1_txen phy transmit data enable when high, indicates that valid data is being transmitted on the mii1_txdn bus. o pl_gpio_92/g16 2, extended mii1_txer phy transmit error when high, indicates a transmit error or carrier extension on the mii1_txdn bus. o pl_gpio_91/g15 2, extended rmii0/rmii1 rmii_mdc management data clock the mac provides timing reference for the rmii_mdio signal through this aperiodic clock. the maximum frequency of this clock is 2.5 mhz.this clock is generated from the application clock (hclk) via a clock divider. o pl_gpio_11/e5 extended mode rmii_mdio management data input/ output io pl_gpio_10/c3 extended mode rmii_ref_clk 50 mhz reference clock input for rmii interface i pl_gpio_22/d6 extended mode table 31. ethernet signals description (continued) signal name description dir. pl_gpio_# / ball number configuration mode (see section 3.4.2 ) spear320s pin description doc id 022508 rev 2 65/113 rmii0_crs_dv phy receive data valid contains the crs (carrier sense) and data valid information of the receive interface. i pl_gpio_14/a2 extended mode rmii0_rx_er phy receive error i pl_gpio_13/a1 extended mode rmii0_rxd0 phy receive data these bits provide the rmii receive data. the validity of the data is qualified with rmii0_crs_dv. i pl_gpio_26/a5 extended mode rmii0_rxd1 pl_gpio_15/b3 extended mode rmii0_tx_en phy transmit data enable when high, indicates that valid data is being transmitted on the rmii_txdn bus o pl_gpio_16/e6 extended mode rmii0_txd0 phy transmit data these bits provide the rmii transmit data. the validity of the data is qualified with rmii0_tx_en. o pl_gpio_27/b6 extended mode rmii0_txd1 pl_gpio_17/c4 extended mode rmii1_crs_dv phy receive data valid contains the crs and data valid information of the receive interface. i pl_gpio_19/a3 extended mode rmii1_rx_er phy receive error i pl_gpio_18/d5 extended mode rmii1_rxd0 phy receive data these bits provide the rmii receive data. the validity of the data is qualified with rmii1_crs_dv. i pl_gpio_24/b5 extended mode rmii1_rxd1 pl_gpio_20/b4 extended mode rmii1_tx_en phy transmit data enable when high, it indicates that valid data is being transmitted on the rmii_txdn bus. o pl_gpio_23/a4 extended mode rmii1_txd0 phy transmit data these bits provide the rmii transmit data. the validity of the data is qualified with rmii1_tx_en. o pl_gpio_25/c6 extended mode rmii1_txd1 pl_gpio_21/c5 extended mode table 31. ethernet signals description (continued) signal name description dir. pl_gpio_# / ball number configuration mode (see section 3.4.2 ) pin description spear320s 66/113 doc id 022508 rev 2 3.5 pl_gpio and pl_clk pin sharing for debug and test modes in some cases the pl_gpio and pl_clk pins may be used in different ways for debugging purposes. there are four different cases (see also ta b l e 32 ): 1. case 0 - all the pl_gpio and pl_clk get values from boundary scan registers during ex-test instruction of jtag . typically, th is configuration is used to verify the correctness of the soldering process during the production flow. the pad (pl_gpio or pl_clk) is driven by the boundary scan register, and disconnected from the i/o function used in functional mode. 2. case 1 - all the pl_gpio and pl_clk maintain their original meaning and the jtag interface is disconnected from the processor. 3. case 2 - all the pl_gpio and pl_clkmaintain their original meaning but the jtag interface is connected to the processor. this configuration is useful during the development phase, but offers only ?static? debug. 4. case 3 - some pl _gpios, as shown in table 32 below, are used to connect the etm9 lines to an external box. this configuration is typically used only during the development phase. it offers a very powe rful debug capability. when the processor reaches a breakpoint it is possible, by a nalyzing the trace buffer, to understand the reason why the processor has reached the break. table 32. ball sharing during debug signals case 0 - boundary scan case 1 - no debug case 2 - static debug case 3 - full debug test_0 0 0 1 0 test_1 0 0 0 1 test_2 0 1 1 1 test_3 0 1 1 1 test_4 1 0 0 0 ntrst ntrst_bscan nc ntrst_arm ntrst_arm tck tck_bscan nc tck_arm tck_arm tms tsm_bscan nc tms_arm tms_arm tdi tdi_bscan nc tdi_arm tdi_arm tdo tdo_bscan nc tdo_arm tdo_arm pl_gpioxxx/ pl_clkx (all pins) used for boundary scan functional mode functional mode pl_gpio97- pl_gpio73 used for debug, refer to table 15: pl_gpio/pl_clk multiplexing s cheme and re s et s tate s on page 43 spear320s electrical characteristics doc id 022508 rev 2 67/113 4 electrical characteristics 4.1 absolute maximum ratings this product contains devices to protect the in puts against damage due to high/low static voltages. however, it is advisable to take normal precaution to avoid application of any voltage higher/lower than the specified maximum/minimum rated voltages. caution: stresses above those listed in ta bl e 3 3 may cause permanent damage to the device. exposure to maximum rating conditions for extended periods may affe ct device reliability. 4.2 maximum power consumption note: the s e value s take into con s ideration the wor s t ca s e s of proce ss variation and voltage range and mu s t be u s ed to de s ign the power s upply s ection of the board. table 33. absolute maximum ratings symbol parameter min max unit v dd 1.2 supply voltage for the core - 0.3 1.44 v v dd 3.3 supply voltage for the i/os - 0.3 3.9 v v dd 2.5 supply voltage for the analog blocks - 0.3 3 v v dd 1.8 supply voltage for the dram interface - 0.3 2.16 v v dd rtc rtc supply voltage -0.3 2.16 v t stg storage temperature -55 150 c table 34. maximum power consumption symbol description max unit i dd(1.2vsupply) current consumption of v dd 1.2 supply voltage for the core 400 ma i dd(1.8vsupply) current consumption of v dd 1.8 supply voltage for the dram interface (1) 1. peak current with linux memory test (50% write and 50% read) plus dma reading memory. 150 ma i dd(rtc) current consumption of rtc supply voltage 8 a i dd(2.5vsupply) current consumption of 2.5v supply voltage for the analog blocks 30 ma i dd(3.3vsupply) current consumption of 3.3v supply voltage for the i/os (2) 2. with 30 logic channels connected to the dev ice and simultaneously switching at 10 mhz. 12 ma p d maximum power consumption (3) 3. based on bench measurements for worst case silic on under worst case operating conditions. devices tested with operating system running, cpu and ddr 2 running at 333 mhz, ddr2 driven by pll2, sdram and all on-chip peripheral s and internal modules enabled. 1.2 v current and power are primarily dependent on the applications running and the use of internal chip functions (dma, usb, ethernet, and so on). 3.3 v current and power are primarily dependent on the capacitive loading, frequency, and utilization of the external buses. 870 mw electrical characte ristics spear320s 68/113 doc id 022508 rev 2 4.3 recommended operating conditions to ensure proper operation of the device, it is highly recommended to follow the conditions shown in the following table. 4.4 overshoot and undershoot this product can support the following values of overshoot and undershoot. if the amplitude of the overshoot/undershoo t increases (decreases), the ratio of overshoot/undershoot width to the pulse width decreases (increases). the formula relating the two is: amplitude of os/us = 0.75*(1- ratio of os (or us) duration with respect to pulse width) note: the value of over s hoot/under s hoot s hould not exceed the value of 0.5 v. however, the duration of the over s hoot/under s hoot can be increa s ed by decrea s ing it s amplitude. table 35. recommended operating conditions symbol parameter min typ max unit v dd 1.2 supply voltage for the core 1.14 1.2 1.3 v v dd 3.3 supply voltage for the i/os 3 3.3 3.6 v v dd 2.5 pll supply voltage (1) 1. for power supply filterin g it is required to add an external ferrite inductor. 2.25 2.5 2.75 v v dd 2.5 oscillator supply voltage 2.25 2.5 2.75 v v dd 1.8 supply voltage for dram interface 1.70 1.8 1.9 v v dd rtc rtc supply voltage 1.3 1.5 1.8 v t a ambient temperature (2) 2. t a to be considered under jesd51 c onditions or equivalent ones. -40 ? 85 c t j junction temperature -40 ? 125 c table 36. overshoot and undershoot specifications parameter 3v3 i/os 2v5 i/os 1v8 i/os amplitude 500 mv 500 mv 500 mv ratio of overshoot (or unders hoot) duration with respect to pulse width 1/3 1/3 1/3 spear320s electrical characteristics doc id 022508 rev 2 69/113 4.5 3.3v i/o characteristics the 3.3 v i/os are compliant with jedec standard jesd8b. table 37. low voltage ttl dc input specification (3 v< v dd <3.6 v) symbol parameter min max unit v il low level input voltage 0.8 v v ih high level input voltage 2 v v hyst schmitt trigger hysteresis 300 800 mv table 38. low voltage ttl dc output specification (3 v< v dd <3.6 v) symbol parameter test condition min max unit v ol low level output voltage i ol = x ma (1) 1. maximum current load (iol) = 10 ma for pl_gpio and pl_clk pins. for the iol max value of dedicated pins, refer to chapter 3: pin de s cription . 0.3 v v oh high level output voltage i oh = -x ma (1) v dd - 0.3 v table 39. pull-up and pull-down characteristics symbol parameter test condition min max unit r pu equivalent pull-up resistance v i = 0 v 29 67 k r pd equivalent pull-down resistance v i = v dde 3v3 29 103 k electrical characte ristics spear320s 70/113 doc id 022508 rev 2 4.6 clocking parameters 4.6.1 master clock (mclk) mclk generated from a crystal oscillator figure 4. mclk crystal connection 1. c l1 and c l2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. to calculate the value of the load capacitance, use the formula given below. formula c l c l1 c l2 u c l1 c l2 + -------------------------- c s + = where c l1 and c l2 are the load capacitors and c s is the circuit stray capacitance. in our application: c l1 = c l2 = c ext table 40. mclk oscillator characteristics symbol parameter conditions min typ max unit f osc_in oscillator frequency 24 (1) 1. a frequency of 24 mhz is mandatory to obtain the re quired frequencies for all cl ocks generated by the usb pll (pll3). 33 (2) 2. at max freq = 33 mhz the esr value has to be less than 20 : mhz esr equivalent series resisistance 50 : gm oscillator transconductance startup 19.8 28.5 ma/v t su startup time stabilized power on mclk_vdd2v5 pin 2 (3) 3. startup time simulated with a 30 mhz crystal. ms v dd 2 v 5 24 mhz cl1 cl2 (1) (1) mclk_xi mclk_xo spear320s electrical characteristics doc id 022508 rev 2 71/113 this implies: c ext = (c l -c s )*2 example: for this example, a rakon xtal003342 24 mhz oscillator has been used. for the rakon xtal003342 crystal, c l = 12 pf with c s = ~3 pf, we have: cext = c l1 = cl2 = 18 pf mclk generated from an external clock source table 41. mclk external user clock source characteristics symbol parameter conditions min typ max unit f mclk_xi external clock source frequency no limitation 24 (1) 33 mhz v mclk_xih mclk_xi input pin high level voltage mclk_vdd2v5 - 0.3 mclk_vdd2v5 v v mclk_xil mclk_xi input pin low level voltage mclk_gndsub 0.3 v ducy (mclk_xi) duty cycle (2) 40 60 % t r(mclk_xi) t f(mclk_xi) mclk_xi input rise and fall time -5% of the clock period +5% of the clock period % c in(mclk_xi) mclk_xi input capacitance 7pf i l(mclk_xi) mclk_xi input leakage current mclk_gndsub v in mclk_vdd2v5 1a 1. a frequency of 24 mhz is mandatory to obtain the requir ed operating frequency for all clocks generated by the usb pll (pll3). 2. an initial delay of 1 s + 2048 f mclk_xi cycles occurs for duty cycle detecti on and internal clock availability. electrical characte ristics spear320s 72/113 doc id 022508 rev 2 4.6.2 real-time clock (rtc) rtc clock generated from a crystal oscillator figure 5. rtc crystal connection 1. c l1 and c l2 are the load capacitors. the value of the capacitors depends on the type of the selected crystal. to calculate the value of the load capacitance, use the formula given below. formula c l c l1 c l2 u c l1 c l2 + -------------------------- c s + = where c l1 and c l2 are the load capacitors and c s is the circuit stray capacitance. in our application: c l1 = c l2 = c ext this implies: c ext = (c l -c s )*2 table 42. rtc oscillator characteristics symbol parameter condition min typ max unit f osc_in oscillator frequency 32.768 khz esr equivalent series resistance 6000 : gm oscillator transconductance startup 5 a/v t su startup time stabilized power on rtc_vdd1v5 pin 17000 f osc_in cycles gn d 32.768 khz cl1 cl2 (1) (1) rtc_xi rtc_xo spear320s electrical characteristics doc id 022508 rev 2 73/113 example: for this example, a fox electronics, nc26l f-327 32.768 khz osc illator has been used. for the fox electronics, nc26lf-327 crystal, c l = 12.5 pf with c s = ~0.1 pf, we have: cext = c l1 = cl2 = 24.8 pf=22 pf rtc clock generated from an external clock source table 43. rtc external user clock source characteristics symbol parameter condition min typ max unit f rtc_xi external clock source frequency 32.768 khz v rtc_xih rtc_xi input pin high level voltage rtc_vdd1v5 - 0.2 rtc_vdd1v5 v v rtc_xil rtc_xi input pin low level voltage rtc_gnd 0.2 v ducy (rtc_xi) duty cycle 40 60 % t r(rtc_xi) tf (rtc_xi) rtc_xi input rise and fall time 50 ns c in(rtc_xi) rtc_xi input capacitance 5pf i l(rtc_xi) rtc_xi input leakage rtc_gnd v in rtc_vdd1v5 1a electrical characte ristics spear320s 74/113 doc id 022508 rev 2 4.7 lpddr and ddr2 pin characteristics table 44. dc characteristics symbol parameter test condition min max unit v il low level input voltage sstl18 -0.3 v ref -0.125 v v ih high level input voltage sstl18 v ref +0.125 v dde 1v8+0.3 v v hyst input voltage hysteresis 200 mv table 45. driver characteristics symbol parameter min typ max unit r o output impedance 45 table 46. on-die termination symbol parameter min typ max unit rt1 termination value of resistance for on die termination 75 rt2 termination value of resistance for on die termination 150 table 47. reference voltage symbol parameter min typ max unit v refin voltage applied to core/pad 0.49 * v dde 0.500 * v dde 0.51 * v dde v spear320s electrical characteristics doc id 022508 rev 2 75/113 4.8 adc pin characteristics table 48. adc pin characteristics symbol parameters min typ max unit f adc_clk adc_clk frequency 3 14 mhz av dd adc supply voltage 2.5 v v refp positive reference voltage 2.5 v v refn negative reference voltage 0 v v iref internal reference voltage 1.95 2 2.05 v t startup startup time 50 s v ain input range (absolute) agnd - 0.3 avdd - 0.3 v conversion range v refn v refp v c ain input capacitance 5 6.4 8 pf r ain input mux resistance (total equivalent sampling resistance) 1.5 2 2.5 k t conv conversion time (f adc_clk =14 mhz) 1s conversion time 13 adc_clk cycles inl integral linearity error 1 lsb dnl differential linearity error 1 lsb electrical characte ristics spear320s 76/113 doc id 022508 rev 2 4.9 power-up sequence it is recommended to power up the power supplies in the order shown in figure 6 . v dd 1.2 is brought up first, followed by v dd 1.8, then v dd 2.5 and finally v dd 3.3 . the minimum time ( t) between each power up is >0 s. figure 6. power-up sequence 4.10 power-down sequence all power supplies can be shut down at the same time. v dd 1.2 v dd 1.8 v dd 2.5 v dd 3.3 power-up sequence t t t spear320s electrical characteristics doc id 022508 rev 2 77/113 4.11 reset release the master reset (mreset) must be released after all the powe r supplies are stable and for a time interval of 2 ms, which is the start-up time of the main oscillato r, and must be asserted low for at least 1 s for warm reset. figure 7. cold reset release figure 8. warm reset release note: see al s o: section 5.2: re s et timing characteri s tic s on page 78 . v dd 1v2 v dd v dd 3 v3 1v 8 mre s et trp(cold)= 2 m s v dd 2 v5 trp(w a rm)= 1 s mre s et timing requirements spear320s 78/113 doc id 022508 rev 2 5 timing requirements this chapter provides the timing requirements for the synchronous and asynchronous ips present in spear320s. the signal transition levels used for timing measurements are: 0.2*vdd and 0.8*vdd. 5.1 external interrupt timing characteristics in legacy modes, all the interrupts are high-level triggered. in extended mode, interrupt trigger polarity is programmabl e as rising or falling edge. 5.2 reset timing characteristics note: warm re s et can be triggered by s oftware by writing any value to the s y s tem controller sysstat regi s ter. table 49. pl_gpio external interrupt input timing symbol description min unit tint minimum width for rising edge interrupt pulse 24 ns table 50. reset timing characteristics symbol description min unit trp(cold) mreset pin active low state duration for cold reset (startup time from all supplies up and stable). see figure 7: cold re s et relea s e on page 77 ) 2ms trp(warm) mreset pin active low state duration for warm reset (minimum pulse width able to reset the device). see figure 8: warm re s et relea s e on page 77 ) 1s spear320s timing requirements doc id 022508 rev 2 79/113 5.3 can timing characteristics the nominal can bit time allows a delay prop_seg to compensate for the physical delay times. for details refer to rm0319, reference manual, spear320s architecture and functionality . ta bl e 51 specifies the delay for the can i/o pads. prop_seg 2 * max node output delay + bus line delay + node input delay table 51. can timing characteristics symbol description max unit t d(rx) can0_rx (pl_gpio32) input delay 5.03 ns can1_rx (pl_gpio30) input delay 6.2 ns t d(tx) can0_tx (pl_gpio33) output delay 9.55 ns can1_tx (pl_gpio31) output delay 10.2 ns timing requirements spear320s 80/113 doc id 022508 rev 2 5.4 clcd timing characteristics the clcd has a wide variety of configurations, and the parameters change accordingly. the timing characterization is performed assuming an output load capacitance of 10 pf on all outputs. figure 9. clcd waveform table 52. clcd timing requirements symbol description min max unit t ck clcp clock period 20.83 41.66 ns t d clcp to clcd output data delay 1 9.5 t ck t d cld[23:0], clac, clle, cllp, clfp, clpower clcp spear320s timing requirements doc id 022508 rev 2 81/113 5.5 ddr2/lpddr timing characteristics the timing parameters listed below are def ined by the jedec standard for ddr memories. ddr memories whose parameters are within the ranges defined in ta b l e 53 , ta b l e 54 and ta bl e 55 can be interfac ed with spear320s. read cycle timing apply to dqs and dq input to spear. write cycle timings refer to dqs and dq output to spear. the timing characterization is performed assuming an output load capacitance of 10 pf on all the ddr pads. 5.5.1 ddr2/lpddr read cycl e timing characteristics figure 10. ddr2/lpddr read cycle waveform table 53. ddr2/lpddr read cy cle timing requirements symbol description min max unit t ck ddr_mem_clkp/clkn cycle time when interfacing ddr2 memory 3 ns lpddr ddr_mem_clkp/clkn cycle time when interfacing lpddr memory 6 t dqsq dqs to dq input setup time 0 0.25t ck +0.4 t qh dqs to dq input hold time 0.25t ck +0.7 0.5t ck t dqsq t qh t qh t dqsq t dqsq ddr_mem_dqs_# ddr_mem_dq_# ddr_mem_clkp/ ddr_mem_clkn t ck timing requirements spear320s 82/113 doc id 022508 rev 2 5.5.2 ddr2/lpddr write cy cle timing characteristics figure 11. ddr2/lpddr write cycle waveform 5.5.3 ddr2/lpddr command timing characteristics figure 12. ddr2/lpddr command waveform table 54. ddr2/lpddr write cy cle timing requirements symbol description min max unit t dqss positive dqs latching edge to associated ck edge -0.5 0.5 ns t ds dq & dqm output setup time relative to dqs 0 0.25t ck ? 0.76 t dh dq & dqm output hold time relative to dqs 0 0.25t ck ? 0.84 ddr_mem_dqs_# ddr_mem_dq_# ddr_mem_clkp/ ddr_mem_clkn t ds t dh t dh t ds t ds t dh t dqss table 55. ddr2/lpddr command timing requirements symbol description min max unit t is address and control output setup time 0 0.5t ck ? 0.5 ns t ih address and control output hold time 0 0.5t ck ? 0.59 t is t ih clk address and commands spear320s timing requirements doc id 022508 rev 2 83/113 5.6 emi timing characteristics figure 13. emi read cycle waveform with acknowledgement on emi_wait note: the value s of t se , t enr , t dcs , t scs are programmable via the emi regi s ter s . note: value s in ta b l e 56 refer to the common internal s ource clock which ha s a period of t hclk = 6 n s . figure 14. emi write cycle waveform with acknowledgement on emi_wait note: the value s of t se , t enw , t dcs , t scs are programmable via the emi regi s ter s . emi_a# emi_byten# emi_d# emi_cen# emi_oe address byte enable data t se t scs t enr t dcs emi_wait t cs->wait t wait table 56. emi timing requirements for read cycle with acknowledgement on wait symbol min t cs->wait t hclk t wait 4*t hclk emi_a# emi_byten# emi_d# emi_cen# emi_we write data byte enable data t se t scs t enw t dcs emi_wait t cs ->t wait t wait timing requirements spear320s 84/113 doc id 022508 rev 2 note: value s in ta b l e 57 refer to the common internal s ource clock which ha s a period of t hclk = 6 n s . figure 15. emi read cycle waveform without acknowledgement on emi_wait note: the value s of t se , t enr , t dcs , t scs are programmable via the emi regi s ter s . figure 16. emi write cycle waveform without acknowledgement on emi_wait note: the value s of t se , t enw , t dcs , t scs are programmable via the emi regi s ter s . table 57. emi timing requirements for write cycle with acknowledgement on wait symbol min t cs->wait t hclk t wait 4*t hclk emi_a# emi_byten# emi_d# emi_cen# emi_oe address byte enable data t se t scs t enr t dcs emi_a# emi_byten# emi_d# emi_cen# emi_we write data byte enable data t se t scs t enw t dcs spear320s timing requirements doc id 022508 rev 2 85/113 5.7 ethernet mii timing characteristics the timing characterization is performed assuming an output load capacitance of 5 pf on the mii tx clock (mii#_txclk) and 10 pf on the other pads. 5.7.1 mii transmit ti ming characteristics figure 17. mii tx waveform note: to calculate the t setup value for the phy, you have to con s ider the next t ck ri s ing edge, s o you have to apply the following formula: t setup = t ck - t max table 58. emi signals timing requirements direction signal name max min unit output emi_a0-emi_a23 8.612293 1.93584 ns emd0-emid15 9.471291 2.260195 emi_ce0 8.764648 2.90581 emi_ce1 7.977348 2.636304 emi_ce2 9.027624 2.930175 emi_ce3 9.29631 3.006315 emi_byten0 9.554388 3.092855 emi_byten1 9.233592 3.038856 emi_re 8.193018 2.680564 emi_we 8.172619 2.80189 input emi_d0-emi_d15 10.8188 1.30245 table 59. mii tx timing requirements symbol description min max unit t ck mii#_txclk clock period 40 40 ns t d mii#_txclk to mii out put data delay 3.34 11.86 t d mii#_txclk mii#_txd0-mii#_txd3, mii#_txen, mii#_txer t ck timing requirements spear320s 86/113 doc id 022508 rev 2 5.7.2 mii receive ti ming characteristics figure 18. mii rx waveform 5.7.3 mdc/mdio timing characteristics figure 19. mdc waveform table 60. mii rx timing requirements symbol description min max unit t ck mii#_txclk clock period 40 40 ns t s setup time requirement for mii receive data 12.5 t h hold time requirement for mii receive data -2 mii#_rxclk t s t h t ck mii#_rxd0-mii#_rxd3 mii#_rxer, mii#_rxdv table 61. mdc timing requirements symbol description min max unit t ck mdc clock period 614.4 614.4 ns t d falling edge of mdc to mdio output delay -2.4 0.64 t s setup time requirement for mdio input 9.6 t h hold time requirement for mdio input -6.6 t d mdc t ck t h t s mdio(input) mdio (output) spear320s timing requirements doc id 022508 rev 2 87/113 note: when mdio i s u s ed a s output the data are launched on the falling edge of the clock a s s hown in figure 19 . 5.8 ethernet rmii timing characteristics 5.8.1 rmii transmit timing characteristics figure 20. rmii tx waveform table 62. rmii tx timing requirements 5.8.2 rmii receive ti ming characteristics figure 21. rmii rx waveform symbol description min max unit t ck rmii_ref_clk period 20 ns t d clock to rmii0_txd output delay 4.28 15.65 clock to rmii1_txd output delay 4.20 15.45 rmii_ref_clk rmiin_txd0, rmiin_txd1 rmiin_tx_en t f t r t ckhigh t cklow t d rmii_ref_clk t h t ckhigh t cklow t f t r t s rmiin_rxd0, rmiin_rxd1 rmiin_crs_dv timing requirements spear320s 88/113 doc id 022508 rev 2 table 63. rmii rx timing requirements symbol description min max unit t ck rmii_ref_clk period 20 ns t s setup time requirement for rmii0 receive data 4.9 setup time requirement for rmii1 receive data 5 t h hold time requirement for rmii0 receive data 0.1 hold time requirement for rmii1 receive data -0.09 spear320s timing requirements doc id 022508 rev 2 89/113 5.9 fsmc timing characteristics the fsmc present in spear320s can interfac e external parallel nand flash memories. the timing characterization is performed using primetime assuming an output load capacitance of 3 pf on the data, 15 pf on fsmc_csx, fsmc_re and fsmc_we and 10 pf on fsmc_addr_le and fsmc_cmd_le. figure 22. output command signal waveform figure 23. output address signal waveform figure 24. in/out data address signal waveform f s mc_c s # f s mc_we f s mc_d# comm a nd t cle t we t io f s mc_cmd_le f s mc_addr_le f s mc_c s # f s mc_we f s mc_d# addre ss t ale t we t io f s mc_c s # f s mc_we f s mc_d# (o u t) d a t a o u t t io f s mc_d# (in) f s mc_re t re -> io t we t re t read t nfio -> ff s timing requirements spear320s 90/113 doc id 022508 rev 2 note: value s in ta bl e 64 refer to the common internal s ource clock which ha s a period of t hclk = 6 n s . table 64. fsmc ti ming requirements symbol min max t cle -3.9 2.8 t ale -4.2 2.6 t we (1) 1. programmable by the tset bi ts in the fsmc registers. (((tset+1) * t hclk ) - 3 ns) (((tset+1) * t hclk ) + 3 ns) t re (1) (((tset+1) * t hclk ) - 3 ns) (((tset+1) * t hclk ) + 3 ns) t io (2) 2. programmable by the thiz bits in the fsmc registers. (((thiz +1) * t hclk ) - 3 ns) (((thiz +1) * t hclk )+ 3 ns) t read (3) 3. programmable by the twait bi ts in the fsmc registers. ((twait+1)* t hclk table 65. fsmc signals timing requirements direction signal name max min data path width unit output fsmc_cmd_le 10.57 3.1 ns fsmc_addr_le 9.5 2.8 fsmc_we 8.5 2.9 fsmc_re 8.4 2.75 fsmc_cs0 9.165836 3.07661 fsmc_cs1 8.473722 2.81431 fsmc_cs2 9.172739 3.02958 fsmc_cs3 9.808426 3.21934 fsmc_d7-fsmc_d0 7.710164 2.298715 8-bit fsmc_d15-fsmc_d8 9.301547 2.420165 8-bit fsmc_d15-fsmc_d0 9.301547 2.298715 16-bit input fsmc_rdy/busy 6.88 1.7 fsmc_d7-fsmc_d0 8.8809 1.18356 8-bit fsmc_d15-fsmc_d8 10.875302 1.37802 8-bit fsmc_d15-fsmc_d0 10.875302 1.18356 16-bit spear320s timing requirements doc id 022508 rev 2 91/113 5.10 gpio/xgpio timing characteristics for edge-sensitive signals, the interrupt line is sampled by flip flops clocked by pclk for gpios and hclk for xgpios, the apb and ahb clocks, normally running at 83 mhz and 166 mhz respectively. the minimum pulse width required for interrupt detection on signal edge is: 3*t pclk (36 ns at 83 mhz) for gpio 3*t hclk (18 ns at 166 mhz) for xgpio timing requirements spear320s 92/113 doc id 022508 rev 2 5.11 i 2 c timing characteristics the timing characterization is performed using primetime assuming an output load capacitance of 10 pf on scl and sda. figure 25. output signal waveform for i 2 c signals the timings of the high and low level of scl (t sclhigh and t scllow ) are programmable. the clock-to-output data delay is: min (t(clk+data)min) = 5.9 max (t(clk+data)max) = 15 the timings shown in figure 25 depend on the programmed value of t sclhigh and t scllow. the values listed in ta b l e 66 to ta b l e 68 have been calculated using the minimum programmable values of : high-speed mode: ic_hs_scl_hcnt= 19 and ic_hs_scl_lcnt= 53 registers fast-speed mode: ic_fs_scl_hcnt= 99 and ic_fs_scl_lcnt= 215 registers standard-speed mode: ic_ss_sc l_hcnt= 664 and ic_ss_scl_lcnt= 780 registers these minimum values depend on the ahb clock frequency, which is 166 mhz. note: 1 a device may internally require a hold time of at lea s t 300 n s for the sda s ignal (referred to the v ihmin of the scl s ignal) to bridge the undefined region of the falling edge of scl (plea s e refer to the i 2 c bu s specification v3-0 jun 2007). however, the sda data hold time in the i 2 c controller of spear320s i s one-clock cycle ba s ed (6 n s with the hclk clock at 166 mhz). thi s time may be in s ufficient for s ome s lave device s . a few s lave device s may not receive the valid addre ss due to the lack of sda hold time and will not acknowledge even if the addre ss i s valid. if the sda data hold time i s in s ufficient, an error may occur. 2 workaround: if a device need s more sda data hold time than one clock cycle, an rc delay circuit i s needed on the sda line a s illu s trated in figure 26 . spear320s timing requirements doc id 022508 rev 2 93/113 figure 26. rc delay circuit table 66. i 2 c timing requirements in high-speed mode parameter min unit t su-sta 140 ns t hd-sta 325 t su-dat 300 t hd-dat 1 t su-sto 620 t hd-sto 4745 table 67. i 2 c timing requirements in fast-speed mode parameter min unit t su-sta 620 ns t hd-sta 602 t su-dat 1270 t hd-dat 1 t su-sto 620 t hd-sto 4745 table 68. i 2 c timing requirements in standard-speed mode parameter min unit t su-sta 4718 ns t hd-sta 3992 t su-dat 4660 t hd-dat 1 t su-sto 4010 t hd-sto 4745 timing requirements spear320s 94/113 doc id 022508 rev 2 5.12 i2s timing characteristics figure 27. i2s waveform 5.13 pwm timing characteristics this section describes the timing characteristics of the four pwm generators. figure 28 shows two pwm waveforms in two example configurations programmed using the pwm registers. figure 28. pwm timing waveforms config. 1: prescalerx = 0, duty_reg_x = 2, period_reg_x = 4. config. 2: prescalerx = 1, duty_reg_x = 2, period_reg_x = 4. calculations (in plck periods) : pwmxduty = (prescalerx +1) * duty_reg_x pwmx period = (prescalerx +1) * (period_reg_x = 1 table 69. i2s timing requirements symbol description min max unit t ck i2s_clk clock period 40 ns t d i2s_clk to i2s_tx output delay 3.8 9 t s setup time requirement for i2s_clk 6 t h hold time requirement for i2s_clk 1 t h i2s_clk i2s_tx, i2s_lr t ckhigh t cklow t s t f t r 2 x pclk 3 x pclk 6 x pclk 4 x pclk t d pclk pwmx (config. 1) pwmx (config. 2) spear320s timing requirements doc id 022508 rev 2 95/113 table 70. pwm timing characterisitics symbol parameter pwm channel external pin min max unit t d pwm path delay from pwm internal output to output on external pin pwm1 pl_gpio_9 4.1 14.3 ns pl_gpio_15 3.9 13.7 pl_gpio_31 4.3 15.1 pl_gpio_38 4.2 14.6 pl_gpio_43 4.0 14.3 pl_gpio_60 4.0 13.8 pl_gpio_89 3.4 10.4 pwm2 pl_gpio_8 4.3 15.2 pl_gpio_14 4.0 14.3 pl_gpio_30 4.3 15.0 pl_gpio_37 4.2 15.0 pl_gpio_42 4.2 14.5 pl_gpio_59 4.2 13.8 pl_gpio_88 3.3 11.0 pwm3 pl_gpio_7 4.4 15.1 pl_gpio_13 4.5 15.8 pl_gpio_29 4.3 15.3 pl_gpio_34 4.5 15.8 pl_gpio_41 3.9 13.8 pl_gpio_58 4.1 14.2 pl_gpio_87 3.4 11.5 pwm4 pl_gpio_6 4.2 14.7 pl_gpio_12 4.0 13.9 pl_gpio_28 4.5 15.3 pl_gpio_40 4.3 15.1 pl_gpio_57 4.4 15.3 pl_gpio_86 3.5 11.9 timing requirements spear320s 96/113 doc id 022508 rev 2 5.14 sd timing characteristics figure 29. sd timing waveform note: in full- s peed mode, the frequency i s 24 mhz (41.6 n s ). the data i s launched at the falling edge of the 24 mhz clock and captured on the clock s ri s ing edge (the effective available time i s alway s 20.8 n s ) table 71. sd timing requirements (high-speed mode, 48 mhz) symbol description min max unit t ck sd_clk clock period 20.8 ? ns t d sd_clk to sd output delay -1.60 10 t s setup time requirement for sd inputs 7.35 t h hold time requirement for sd inputs 0.19 table 72. sd timing requirements (full-speed mode, 24 mhz) symbol description min max unit t ck sd_clk clock period 41.6 ? ns t ck-half sd_clk half period 20.8 t d sd_clk to sd output delay -0.40 10 t s setup time requirement for sd inputs 7.35 t h hold time requirement for sd inputs 0.19 t ck sd_clk sd_dat# sd_wp sd_cmd sd_led sd_cd sd_dat# (input) t s t h d t spear320s timing requirements doc id 022508 rev 2 97/113 5.15 smi timing characteristics figure 30. smi input/output waveform table 73. smi timing requirements symbol description min max unit t ck smi clock period 20 50 ns t d smi_clk to smi_dataout output delay -2.96 3.05 t s setup requirement for smi_datain 8.05 t h hold requirement for smi_datain -2.53 t csf minimum and maximum delay of falling edge of smi_cs_0 , 1 with regard to smi_clk -3.0 2.9 t csr minimum and maximum delay of rising edge of smi_cs_0 , 1 with regard to smi_clk -2.8 2.8 smi_clk smi_datain t s t h t ck t d t csf t csr smi_dataout smi_cs_0,1 timing requirements spear320s 98/113 doc id 022508 rev 2 5.16 ssp timing characteristics this section describes the timing characte ristics of the synchronous serial port. note: note:the characterization of the ssp ha s been done u s ing the spi protocol. figure 31. ssp_sck waveform the clock polarity parameter (spo) indicates the state of the clock signal when it is idle. this can be programmed in the sspcr0 register. spo= 0 the clock idle state is low. spo= 1 the clock idle state is high. 5.16.1 spi master mode timings ssp_sck is the spi output clock. t pclk is the clock period of the pclk internal clock. figure 32. spi master mode external timing waveform ( sph= 0, spo =0 ) t clkhigh t clklow t clk ss p_ s ck ( s po=0) ss p_ s ck ( s po=1) data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=0) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d2 t d1 t d 3 spear320s timing requirements doc id 022508 rev 2 99/113 table 74. spi master mode timing characteristics (sph = 0, spo=0) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) rising edge ssp0 7.8 ns ssp1 16 ssp2 15.55 t h hold time, miso (inp ut) valid after ssp_sck (output) rising edge ssp0 -2.7 ssp1 -4 ssp2 -4.6 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) rising edge ssp0 t ssp_sck -10 t ssp_sck -3 ns ssp1 t ssp_sck -6.4 t ssp_sck -0.9 ssp2 t ssp_sck -5.87 t ssp_sck -0.03 t d2 delay time, ssp_sck (o utput) falli ng edge to mosi (output) transition ssp0 2.7 9.5 ns ssp1 0.57 5.34 ssp2 0.2 5.53 t d3 delay time, ssp_sck (o utput) falli ng edge to ssp_ss#n (output) rising edge ssp0 (t ssp_sck /2)+ 3 (t ssp_sck /2) +8 ssp1 (t ssp_sck /2)+ 0.9 (t ssp_sck /2) +6.4 ssp2 (t ssp_sck /2)-0.03 (t ssp_sck /2) +5.87 timing requirements spear320s 100/113 doc id 022508 rev 2 figure 33. spi master mode external timing waveform ( sph= 0, spo =1 ) data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=1) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t d1 t h t d 3 t d2 table 75. spi master mode timing characteristics (sph = 0, spo=1) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) falling edge ssp0 7.8 ns ssp1 16 ssp2 15.55 t h hold time, miso (inp ut) valid after ssp_sck (output) falling edge ssp0 -2.7 ssp1 -4 ssp2 -4.6 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) falling edge ssp0 t ssp_sck -10 t ssp_sck -3 ns ssp1 t ssp_sck -6.4 t ssp_sck -0.9 ssp2 t ssp_sck -5.87 t ssp_sck -0.03 t d2 delay time, ssp_sck (output) rising edge to mosi (output) transition ssp0 2.7 9.5 ns ssp1 0.57 5.34 ssp2 0.2 5.53 t d3 delay time, ssp_sck (output) rising edge to ssp_ss#n (output) rising edge ssp0 (t ssp_sck /2)+ 3 (t ssp_sck /2) +8 ssp1 (t ssp_sck /2)+ 0.9 (t ssp_sck /2) +6.4 ssp2 (t ssp_sck /2)-0.03 (t ssp_sck /2) +5.87 spear320s timing requirements doc id 022508 rev 2 101/113 figure 34. spi master mode external timing waveform (sph = 1, spo = 0) data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=0) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d2 t d 3 t d1 table 76. spi master mode timing characteristics (sph = 1, spo=0) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) falling edge ssp0 7.8 ns ssp1 16 ssp2 15.55 t h hold time, miso (inp ut) valid after ssp_sck (output) falling edge ssp0 -2.7 ssp1 -4 ssp2 -4.6 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) falling edge ssp0 (t ssp_sck /2)-10 (t ssp_sck /2)-3 ns ssp1 (t ssp_sck /2)-6.4 (t ssp_sck /2)-0.9 ssp2 (t ssp_sck /2)-5.87 (t ssp_sck /2)-0.03 t d2 delay time, ssp_sck (output) rising edge to mosi (output) transition ssp0 2.7 9.5 ns ssp1 0.57 5.34 ssp2 0.2 5.53 t d3 delay time, ssp_sck (output) rising edge to ssp_ss#n (output) rising edge ssp0 t ssp_sck + 3 (t ssp_sck +10 ssp1 t ssp_sck + 0.9 (t ssp_sck +6.4 ssp2 t ssp_sck -0.03 t ssp_sck +5.87 timing requirements spear320s 102/113 doc id 022508 rev 2 figure 35. spi master mode external timing waveform (sph = 1, spo = 1) data m s b in l s b in l s b out data m s b out ss p_ ss #n ss p_ s ck ( s po=1) ss p_mi s o (inp u t) ss p_mo s i (o u tp u t) t s u t h t d1 t d2 t d 3 table 77. spi master mode timing characteristics (sph = 1, spo=1) symbol parameters min max unit t su setup time, miso (input) valid before ssp_sck (output) rising edge ssp0 7.8 ns ssp1 16 ssp2 15.55 t h hold time, miso (inp ut) valid after ssp_sck (output) rising edge ssp0 -2.7 ssp1 -4 ssp2 -4.6 t d1 delay time, ssp_ss#n (output) falling edge to first ssp_sck (output) rising edge ssp0 (t ssp_sck /2)-10 (t ssp_sck /2)-3 ns ssp1 (t ssp_sck /2)-6.4 (t ssp_sck /2)-0.9 ssp2 (t ssp_sck /2)-5.87 (t ssp_sck /2)-0.03 t d2 delay time, ssp_sck (o utput) falli ng edge to mosi (output) transition ssp0 2.7 9.5 ns ssp1 0.57 5.34 ssp2 0.2 5.53 t d3 delay time, ssp_sck (output) rising edge to ssp_ss#n (output) rising edge ssp0 t ssp_sck + 3 (t ssp_sck +10 ssp1 t ssp_sck + 0.9 (t ssp_sck +6.4 ssp2 t ssp_sck -0.03 t ssp_sck +5.87 spear320s timing requirements doc id 022508 rev 2 103/113 5.16.2 spi slave mode timings 5.17 spp timing characteristics this section describes the ti ming characteristics of the standard parallel port (spp). figure 36. spp timing waveform 5.18 uart timing characteristics figure 37. uart transmit and receive waveform table 78. ssp timing characteristics (slave mode) symbol parameters min max unit t ssp_clk ssp_clk_in input clock period t pclk *12 254*256*t pclk ns t ssp_clkhigh ssp_sck high pulse t ssp_clk /2 t ssp_clklow ssp_sck low pulse t ssp_clk /2 t su data input setup time 4*t pclk t h data input hold time 0 t d data output delay 3*t pclk 4*t pclk t strb spp_datax valid data t ds t dv t selin spp_selinn spp_strbn spp_ackn t ack spp_busy data read by cpu t sa t sb t selin t init spp_autofdn auto line feed (can be used as 9th data/parity bit) spp_initn b0 b1 start bit uarttxd uartrxd stop bit b2 -- - b7 pbit t bit t bit t bit t bit timing requirements spear320s 104/113 doc id 022508 rev 2 the above min. and max. values allow a deviation of 1 baud cycle in a single bit time. the accumulated deviation of a uart character frame must not exceed 3/(16*f baudrate ). for information related to baud rate generation refer to: section 2.12: a s ynchronou s s erial port s (uart) rm0321, reference manual, spear320s addre ss map and regi s ter s figure 38. rs485_oe transmit and receive waveform table 79. uart transmit timing characteristics symbol parameters min max unit f baudrate uart1 .. uart6 baud rate 6 (1) 1. maximum baudrate = 6 mbps provided that uart clk is within a frequency range greater than 96 mhz and less than 5/3 pclk. mbps uart0 baud rate 3 t bit uart duration of transmit data bit (b0..b7), parity bit (pbit), start bit, stop bits (2) 2. t uartclk = 1/f uartclk with f uartclk in mhz 1/f baudrate - t uartclk -1 1/f baudrate + t uartclk +1 ns table 80. uart receive timing characteristics symbol parameter conditions min max unit t bit pulse duration of receive data (b0 ..b7), parity bit (pbit), start bit, stop bits (1) 1. the time margin is with respect to a single bit accu mulation and not with respect to the whole uart frame. the start bit is sampled after the 8th baud cycle after a low is detected at inpu t, subsequently, each bit is sampled at consecutive 16 baud cycles. baudrate = 6 mbps 1/f baudrate - (t uartclk /2) 1/f baudrate + (t uartclk /2) ns 1/f baudrate -1/ (16*f baudrate ) 1/f baudrate + (16*f baudrate ) ns uarttxd start bit stop bit b pbit uartrxd start bit stop bit b pbit t d1 t d2 rs485_oe spear320s timing requirements doc id 022508 rev 2 105/113 note: 1 the time value depend s upon the cpu frequency to write and read regi s ter s . 2 it al s o depend s on the uart clock frequency u s ed to s et it s flag regi s ter bit to indicate the end of tran s mi ss ion. for example: for t d2, the above values are with respect to 83 mhz pclk and uartclk 83 mhz. table 81. rs485_oe transmit and receive timing characteristics symbol parameters min max unit t d1 delay from oe enable till uart first bit transmission 500 ns t d2 delay from uart last bit transmission till oe enable 900 ns package information spear320s 106/113 doc id 022508 rev 2 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www. s t.com . ecopack ? is an st trademark. table 82. lfbga289 (15 x 15 x 1.7 mm) mechanical data dim. mm inches min. type max. min. type max. a 1.700 0.0669 a1 0.270 0.0106 a2 0.985 0.0387 a3 0.200 0.0078 a4 0.800 0.0315 b 0.450 0.500 0.550 0.0177 0.0197 0.0217 d 14.850 15.000 15.150 0.5846 0.5906 0.5965 d1 12.800 0.5039 e 14.850 15.000 15.150 0.5846 0.5906 0.5965 e1 12.800 0.5039 e 0.800 0.0315 f 1.100 0.0433 ddd 0.200 0.0078 eee 0.150 0.0059 fff 0.080 0.0031 spear320s package information doc id 022508 rev 2 107/113 figure 39. lfbga289 package dimensions table 83. lfbga289 package thermal characteristics symbol parameter value unit ja (1) 1. measured on jesd51 2s2p test board. thermal resistance junction-to-ambient 30 c/w jb thermal resistance junction-to-board 21 jc thermal resistance junction-to-case 13.5 jc junction-to-case thermal characterisation parameter 0.48 acronyms spear320s 108/113 doc id 022508 rev 2 appendix a acronyms table 84. list of acronyms acronym definition adc analog-to-digital converter aes advanced encryption standard ahb amba high speed bus amba advanced microcontroller bus architecture apb advanced peripheral bus bist built-in self test can controller area network cbc cipher block chaining cmos complimentary metal-oxide semiconductor cpu central processing unit crc cyclic redundancy check ddr double data rate des data encryption standard dll delay locked loop (when applied to ddr memories) dma direct memory access emi external memory interface etm embedded trace macrocell fifo first-in-first-out fiq fast interrupt request fpga field programmable gate array fsmc flexible static memory controller gb giga bytes gpio general purpose input / output hlos high-level operating system hmi human machine interface hw hardware irda infrared data association irq interrupt request jpeg joint photographic experts group jtag joint test action group kb kilo bytes lcd liquid color display spear320s acronyms doc id 022508 rev 2 109/113 lsb least significant bit mac media access control mb mega bytes mcu microcontroller unit md5 message digest 5 mii media independent interface mmu memory management unit msb most significant bit phy physical (device, transceiver, layer) pll phase locked loop pwm pulse width modulation ram random access memory ras reconfigurable array subsystem rf radio frequency rfu reserved for future use risc reduced instruction set computing rmii reduced media independent interface rom read only memory rtc real-time clock rtos real-time operating system rx receive sha-1 secure hash algorithm smi serial memory interface soc system-on-chip spi serial peripheral interface spp standard parallel port sram static ram ssp synchronous serial port sw software tcm tightly coupled memory tft thin film transistor, a display technology tx transmit uart universal asyn chronous receiver transmitter usb universal serial bus table 84. list of acronyms (continued) acronym definition acronyms spear320s 110/113 doc id 022508 rev 2 vic vectored interrupt controller wdt watchdog timer table 84. list of acronyms (continued) acronym definition spear320s revision history doc id 022508 rev 2 111/113 revision history table 85. document revision history date revision changes 5-apr-2012 1 initial release. 27-sep-2012 2 figure 1: spear320s architectural block diagram : replaced ?4 kb sram? by ?8 kb sram?. section 2.2: internal memorie s (bootrom/sram) : added ?boot from uart0? and ?boot from ether net mii0? to the list of bootstrap modes. section 2.25: sy s tem controller (sysctr) : replaced ?a low-speed oscillator? by ?a crystal oscillator (24 mhz) or a low-frequency oscillator (32 khz)? in doze mode description. ta bl e 3 2 : b a l l s haring during debug : modified the configuration for pins test_2, test_3 and test_4. section 3.4.2: extended mode: rmii automation networking mode revised descriptions of each mode. section 3.4.5: boot pin s added description of h[7:0] pins ethernet mii0 boot and bypass mode. updated figure 3: hierarchical multiplexing s cheme added note on i/o direction below table 13: pl_gpio / pl_clk pin s de s cription chaged order of columns and added reset states to table 15: pl_gpio/pl_clk multiplexing s cheme and re s et s tate s added section 3.5: pl_gpio and pl_clk pin s haring for debug and te s t mode s table 8: debug pin s de s cription : ? replaced ?test configuration ports? by ?debug mode configuration ports? ? deleted ?for functional mode, they have to be set to zero? for pins test_0 to test_4. ? added a cross-reference. ? added bypass mode to table 14: boot pin s de s cription section 4.6: clocking parameter s : ? added ta bl e 4 0 : m c l k o s cillator characteri s tic s and new section : mclk generated from a cry s tal o s cillator . added ta b l e 4 2 : rt c o s cillator characteri s tic s and new section : rtc clock generated from an external clock s ource . section 4.11: re s et relea s e : ? updated the introduction. ? renamed and updated figure 7: cold re s et relea s e . ? added new figure 8: warm re s et relea s e . ta bl e 5 0 : r e s et timing characteri s tic s : added new row for warm reset. revision history spear320s 112/113 doc id 022508 rev 2 27-sep-2012 2 (cont?d) added section 5.3: can timing characteri s tic s updated section 5.5: ddr2/lpddr timing characteri s tic s section 5.7.3: mdc/mdio timing characteri s tic s , corrected td min updated table 62: rmii tx timing requirement s section 5.11: i2c timing characteri s tic s added note and diagram of rc circuit. added section 5.13: pwm timing characteri s tic s added section 5.18: uart timing characteri s tic s table 83: lfbga289 package thermal characteri s tic s : ? modified j a, j b, j c values. ? added jc value. table 85. document revision history (continued) date revision changes spear320s doc id 022508 rev 2 113/113 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for 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